公开(公告)号：US11640537B2

公开(公告)日：2023-05-02

申请号：US16378107

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Krishnakumar Nair ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Bijoy Pazhanimala ,  Ambili Vengallur

IPC: G06N3/10

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

公开(公告)号：US11544191B2

公开(公告)日：2023-01-03

申请号：US16830457

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Ambili Vengallur ,  Bharat Daga ,  Pradeep K. Janedula ,  Bijoy Pazhanimala ,  Aravind Babu Srinivasan

IPC: G06F12/0811 ,  G06N3/08 ,  G06F7/544

Abstract: Hardware accelerators for accelerated grouped convolution operations. A first buffer of a hardware accelerator may receive a first row of an input feature map (IFM) from a memory. A first group comprising a plurality of tiles may receive a first row of the IFM. A plurality of processing elements of the first group may compute a portion of a first row of an output feature map (OFM) based on the first row of the IFM and a kernel. A second buffer of the accelerator may receive a third row of the IFM from the memory. A second group comprising a plurality of tiles may receive the third row of the IFM. A plurality of processing elements of the second group may compute a portion of a third row of the OFM based on the third row of the IFM and the kernel as part of a grouped convolution operation.

公开(公告)号：US20200320403A1

公开(公告)日：2020-10-08

申请号：US16378107

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Krishnakumar Nair ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Bijoy Pazhanimala ,  Ambili Vengallur

IPC: G06N3/10

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

公开(公告)号：US10769526B2

公开(公告)日：2020-09-08

申请号：US15960851

申请日：2018-04-24

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Ambili Vengallur

IPC: G06F7/544 ,  G06F17/16 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises accelerator circuitry including a first set of processing elements to perform first computations including matrix multiplication operations, a second set of processing elements to perform second computations including sum of elements of weights and offset multiply operations and a third set of processing elements to perform third computations including sum of elements of inputs and offset multiply operations, wherein the second and third computations are performed in parallel with the first computations.