公开(公告)号：US20240118892A1

公开(公告)日：2024-04-11

申请号：US18543357

申请日：2023-12-18

Applicant: Intel Corporation

Inventor： Swagath VENKATARAMANI ,  Dipankar DAS ,  Ashish RANJAN ,  Subarno BANERJEE ,  Sasikanth AVANCHA ,  Ashok JAGANNATHAN ,  Ajaya V. DURG ,  Dheemanth NAGARAJ ,  Bharat KAUL ,  Anand RAGHUNATHAN

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06N3/04 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06F9/30145 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/52 ,  G06N3/04 ,  G06N3/063 ,  G06N3/084

Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.

公开(公告)号：US20220198110A1

公开(公告)日：2022-06-23

申请号：US17132891

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shanker Raman NAGESH ,  Ashok JAGANNATHAN

IPC: G06F30/33

Abstract: A method is described. The method includes maintaining a synchronized count value in each of a plurality of logic chips within a same package. The method includes comparing the count value against a same looked for count value in each of the plurality of logic chips. The method includes each of the plurality of logic chips recording in its respective local memory at least some of its state information in response to each of the plurality of logic chips recognizing within a same cycle that the count value has reached the same looked for count value.

公开(公告)号：US20190303743A1

公开(公告)日：2019-10-03

申请号：US16317497

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Swagath VENKATARAMANI ,  Dipankar DAS ,  Ashish RANJAN ,  Subarno BANERJEE ,  Sasikanth AVANCHA ,  Ashok JAGANNATHAN ,  Ajaya V. DURG ,  Dheemanth NAGARAJ ,  Bharat KAUL ,  Anand RAGHUNATHAN

IPC: G06N3/04 ,  G06N3/08

Abstract: Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.