公开(公告)号：US20240364643A1

公开(公告)日：2024-10-31

申请号：US18141154

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： Sandeep K. Jain ,  Akhilesh Thyagaturu ,  Joshua B. Fryman ,  Poornima Lalwaney ,  Vinodh Gopal ,  Brian Paul Johnson

IPC: H04L49/90 ,  H04L47/32 ,  H04L49/118

CPC classification number: H04L49/9068 ,  H04L47/32 ,  H04L49/118

Abstract: Techniques for processing packets on a network interface controller (NIC) with memory chiplets are disclosed. In an illustrative embodiment, a NIC includes a disaggregated memory with several high-bandwidth memory chiplets spread out in various locations on the NIC. The disaggregated nature of the memory can improve latency, throughput, and scalability as well as improve thermal performance by distributing heat generation to different locations on the NIC. In use, ports of the NIC can be configured to identify packets associated with certain flows and direct those packets to queues on the NIC. Direct memory access circuitry can copy the packets from queues on the NIC to queues on the system memory. This chain of copying packets from the port to the system memory creates a kind of virtual circuit, delivering packets directly to applications with low latency.