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公开(公告)号:US12126394B2
公开(公告)日:2024-10-22
申请号:US17767871
申请日:2020-04-14
Applicant: Galactic Telecom Group, LLC
Inventor: James Kirunda Kakaire
IPC: H04B17/318 , H04L49/111 , H04L49/90 , H04W36/32
CPC classification number: H04B17/318 , H04L49/111 , H04L49/9068 , H04W36/326
Abstract: A Mobile Wireless Broadband Network Interface Card (MWBNIC) for networking electronic devices on a wireless broadband spectrum. The MWBNIC is built into electronic devices as a connecting modem or plugged in via external device ports such as USB. A microprocessor chip attached to a circuit board with a network packet controller coupled to a dedicated cache memory utilized to temporarily store the last N data packets from a node for networking WIFI maintains packet continuity. The network comes with protocols that control packet processing. The MWBNIC embedded packet control protocol (PCP) pushes, pops, compares and deletes packets from cache when a device is in motion. The PCP is connected to a mechanism for determining bandwidth on nodes, another mechanism for switching frequency to that of the next K-Node to connect to and a pre-determined connectivity data set that directly connects the modem in motion are means for networking broadband spectrum.
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公开(公告)号:US20240045814A1
公开(公告)日:2024-02-08
申请号:US18243493
申请日:2023-09-07
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Daniel Rivas Barragan , Kshitij A. Doshi , Mark A. Schmisseur
IPC: G06F13/16 , G06F12/0817 , H04L12/46 , C07F15/00 , G06F12/0831 , G06F12/1018 , H04L49/90
CPC classification number: G06F13/1663 , G06F12/082 , H04L12/4625 , G06F12/0822 , C07F15/0033 , G06F12/0831 , G06F12/1018 , H04L49/9068 , G06F2212/1024 , G06F2212/621
Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
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公开(公告)号:US11838319B2
公开(公告)日:2023-12-05
申请号:US17734822
申请日:2022-05-02
Applicant: Fortinet, Inc.
IPC: H04L9/40 , H04L69/329 , H04L43/16 , H04L49/90 , H04L45/748 , H04L67/02
CPC classification number: H04L63/1458 , H04L43/16 , H04L45/748 , H04L49/9068 , H04L63/1433 , H04L67/02 , H04L69/329
Abstract: Systems and methods for providing an integrated or Smart NIC-based hardware accelerator for a network security device to facilitate identification and mitigation of DoS attacks is provided. According to one embodiment, a processor of a network security device receives an application layer protocol request from a client, directed to a domain hosted by various servers and protected by the network security device. The application layer protocol request is parsed to extract a domain name and a path string. The hardware acceleration sub-system updates rate-based counters based on the application layer protocol request by performing a longest prefix match on the domain name and the path string. When a rate threshold associated with the rate-based counters is exceeded, a challenge message is created and transmitted to the client, having embedded therein the application layer protocol request; otherwise the application layer protocol request is allowed to pass through the network security device.
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公开(公告)号:US20230362105A1
公开(公告)日:2023-11-09
申请号:US18222385
申请日:2023-07-14
Applicant: Nicira, Inc.
Inventor: Ronghua Zhang , Yong Wang , Teemu Koponen , Xinhua Hong
IPC: H04L49/25 , H04L12/66 , H04L45/64 , H04L69/321 , H04L12/46 , H04L41/5041 , H04L45/74 , H04L67/63 , H04L67/568 , H04L67/1001 , H04L45/00 , H04L49/00 , H04L49/90 , H04L45/586 , H04L45/02 , H04L45/42 , H04L45/44 , H04L41/0654 , H04L45/122 , H04L45/745 , H04L61/2585 , H04L41/14 , H04L69/326 , H04L69/329 , H04L47/19 , H04L45/302 , H04L43/08 , H04L43/106 , H04L49/354 , H04L67/1038
CPC classification number: H04L49/25 , H04L12/66 , H04L45/64 , H04L69/321 , H04L12/4654 , H04L12/4633 , H04L41/5041 , H04L45/742 , H04L67/63 , H04L67/568 , H04L67/1001 , H04L45/72 , H04L49/3009 , H04L49/3063 , H04L49/9068 , H04L45/74 , H04L45/586 , H04L45/02 , H04L45/42 , H04L45/44 , H04L41/0654 , H04L45/122 , H04L45/745 , H04L61/2585 , H04L41/145 , H04L69/326 , H04L69/329 , H04L47/19 , H04L45/306 , H04L43/08 , H04L43/106 , H04L49/354 , H04L67/1038 , H04L61/103
Abstract: A novel design of a gateway that handles traffic in and out of a network by using a datapath pipeline is provided. The datapath pipeline includes multiple stages for performing various data-plane packet-processing operations at the edge of the network. The processing stages include centralized routing stages and distributed routing stages. The processing stages can include service-providing stages such as NAT and firewall. The gateway caches the result previous packet operations and reapplies the result to subsequent packets that meet certain criteria. For packets that do not have applicable or valid result from previous packet processing operations, the gateway datapath daemon executes the pipelined packet processing stages and records a set of data from each stage of the pipeline and synthesizes those data into a cache entry for subsequent packets.
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公开(公告)号:US11809338B2
公开(公告)日:2023-11-07
申请号:US17492928
申请日:2021-10-04
Applicant: Intel Corporation
Inventor: Francesc Guim Bernat , Daniel Rivas Barragan , Kshitij A. Doshi , Mark A. Schmisseur
IPC: G06F12/00 , G06F13/16 , G06F12/0817 , H04L12/46 , C07F15/00 , G06F12/0831 , G06F12/1018 , H04L49/90
CPC classification number: G06F13/1663 , C07F15/0033 , G06F12/082 , G06F12/0822 , G06F12/0831 , G06F12/1018 , H04L12/4625 , H04L49/9068 , G06F2212/1024 , G06F2212/621
Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
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公开(公告)号:US20230325343A1
公开(公告)日:2023-10-12
申请号:US18206079
申请日:2023-06-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sompong Paul OLARIG
IPC: G06F13/42 , G06F15/16 , G06F13/40 , G06F15/173 , H04L49/90
CPC classification number: G06F13/4282 , G06F15/161 , G06F13/4022 , G06F15/17331 , H04L49/9068
Abstract: A device that may configure itself is disclosed. The device may include an interface that may be used for communications with a chassis. The interface may support a plurality of transport protocols. The device may include a Vital Product Data (VPD) reading logic to read a VPD from the chassis and a built-in self-configuration logic to configure the interface to use one of the transport protocols and to disable alternative transport protocols, responsive to the VPD.
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公开(公告)号:US11706151B2
公开(公告)日:2023-07-18
申请号:US17566381
申请日:2021-12-30
Applicant: Intel Corporation
Inventor: Anil Vasudevan , Kiran A. Patil , Arun Chekhov Ilango
IPC: H04L47/50 , H04L47/24 , H04L47/2475 , H04L49/90 , H04L43/10
CPC classification number: H04L47/50 , H04L47/24 , H04L47/2475 , H04L49/90 , H04L49/9068 , H04L43/10
Abstract: There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet; and assign the incoming network packet to the queue.
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公开(公告)号:US20180131641A1
公开(公告)日:2018-05-10
申请号:US15595150
申请日:2017-05-15
Inventor: Hyuck Yoo , Cheolho Hong , Kyoungwoon Lee
IPC: H04L12/861 , H04L12/883 , H04L12/863
CPC classification number: H04L49/9068 , H04L12/56 , H04L47/621 , H04L49/9005 , H04L49/9021 , H04W88/02
Abstract: A high-speed packet processing system and a method of controlling the system are disclosed. The high-speed packet processing system includes: a network interface card configured to receive or transmit packets; a memory which is accessible by an operating system, and which includes at least one or more data buffers and a single dedicated head (dedicated skb) decoupled from the data buffers, where the data buffers are pre-allocated in correspondence to the packets to allow storing of the packets, and the single dedicated head is connected to the data buffers sequentially in correspondence to the packets; and a packet processing unit configured to sequentially connect the single dedicated head with the data buffers and store the packets sequentially in the data buffers corresponding to reception (Rx) descriptors based on the reception (Rx) descriptors designated in correspondence to the packets, when the packets are received.
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公开(公告)号:US09838342B2
公开(公告)日:2017-12-05
申请号:US13895177
申请日:2013-05-15
Applicant: Dell Products L.P.
Inventor: Umesh Sunnapu
IPC: G06F15/16 , H04L12/861 , H04L12/803 , H04L12/24
CPC classification number: H04L49/9068 , H04L41/0886 , H04L47/125
Abstract: A network connection teaming system includes a processing system coupled to a memory system in an IHS chassis. The memory system is operable to receive instruction that, when executed by the processing system, cause the processing system to provide an operating system (OS). At least one network interface controller (NIC) including a plurality of network connections is located in the IHS chassis and coupled to the processing system. The NIC(s) are not directly visible to an OS provided to by the processing system. A NIC teaming controller is coupled between the processing system and the NIC(s). The NIC teaming controller includes a plurality of hardware connections that are configurable to team the plurality of network connections included on the NIC(s) to provide at least one teamed network connection. An OS provided by the processing system is presented the at least one teamed network connection by the NIC teaming controller.
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公开(公告)号:US09692698B2
公开(公告)日:2017-06-27
申请号:US14320386
申请日:2014-06-30
Applicant: Nicira, Inc.
Inventor: Shoby Cherian , Raghavendra Subbarao Narahari Venkata , Tanuja Ingale
IPC: H04L12/28 , H04L12/741 , H04L29/06 , H04L12/931 , H04L12/46 , G06F9/455 , H04L12/861 , H04L29/12
CPC classification number: H04L12/4633 , G06F9/45558 , G06F2009/45595 , H04L45/745 , H04L49/354 , H04L49/9068 , H04L61/103 , H04L61/6022 , H04L69/22 , H04L2012/4629
Abstract: A method for offloading packet encapsulation for an overlay network is provided. The method, at a virtualization software of a host, sends a mapping table of the overlay network to a physical network interface controller (NIC) associated with the host. The mapping table maps the identification of each of a set of virtual machine (VM) of a tenant on the host to an identification of a tunnel on the overlay network. The method, at the virtualization software, receives a packet from a VM of the tenant. The method sends the packet to the physical NIC. The method, at the physical NIC, encapsulates the packet for transmission over the overlay network by using the mapping table. The method of claim also tags the packet by the virtualization software as a packet that requires encapsulation for transmission in the overlay network prior to sending the packet to the physical NIC.
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