公开(公告)号：US10157142B2

公开(公告)日：2018-12-18

申请号：US15280965

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Ashok Raj ,  Sivakumar Radhakrishnan ,  Dan J. Williams ,  Vishal Verma ,  Narayan Ranganathan ,  Chet R. Douglas

IPC: G06F12/00 ,  G06F12/10 ,  G06F3/06

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

公开(公告)号：US20210263855A1

公开(公告)日：2021-08-26

申请号：US17223113

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

公开(公告)号：US20180189177A1

公开(公告)日：2018-07-05

申请号：US15394667

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Steen Larsen ,  Chet R. Douglas

IPC: G06F12/06 ,  H04L29/08 ,  G06F12/0802

CPC classification number: G06F12/06 ,  G06F11/1446 ,  G06F12/0802 ,  G06F2212/60 ,  H04L67/06 ,  H04L67/1095 ,  H04L67/2842

Abstract: Apparatus and method for distributed management of data objects in a network of compute nodes are disclosed herein. A first compute node interface may be communicatively coupled to a first compute node to receive a request from the first compute node for at least a portion of a particular version of a data object, wherein the first compute node interface is to include mapping information and logic, wherein the logic is to redirect the request to a second compute node interface associated with a second compute node when the second compute node is mapped to a plurality of data object addresses that includes an address associated with the data object in accordance with the mapping information, and wherein the first compute node is to receive, as a response to the request, the at least a portion of the particular version of the data object from a third compute node interface associated with a third compute node.

公开(公告)号：US11580029B2

公开(公告)日：2023-02-14

申请号：US17223113

申请日：2021-04-06

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02

Abstract: A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.

公开(公告)号：US10997082B2

公开(公告)日：2021-05-04

申请号：US16451086

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.

公开(公告)号：US20190310944A1

公开(公告)日：2019-10-10

申请号：US16451086

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Andy Rudoff ,  Tiffany J. Kasanicky ,  Wei P. Chen ,  Rajat Agarwal ,  Chet R. Douglas

IPC: G06F12/0891 ,  G06F12/02

Abstract: According to various aspects, a memory system may include: a memory having a memory address space associated therewith to access the memory; a cache memory assigned to the memory; one or more processors configured to generate a dummy address space in addition to the memory address space, each address of the dummy address space being distinct from any address of the memory address space, and generate one or more invalid cache entries in the cache memory, the one or more invalid cache entries referencing one or more dummy addresses of the dummy address space.