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    Logging errors in error handling devices in a system
    3.
    发明授权
    Logging errors in error handling devices in a system 有权

    公开(公告)号：US10802903B2

    公开(公告)日：2020-10-13

    申请号：US15846170

    申请日：2017-12-18

    Applicant: INTEL CORPORATION

    Inventor： Sivakumar Radhakrishnan ,  Malay Trivedi ,  Jayasekhar Tholiyil ,  Erik A. McShane ,  Roger W. Liu ,  Mahesh S. Natu

    IPC: G06F11/07

    Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

    Offload data transfer engine for a block data transfer interface
    5.
    发明授权
    Offload data transfer engine for a block data transfer interface 有权

    公开(公告)号：US10157142B2

    公开(公告)日：2018-12-18

    申请号：US15280965

    申请日：2016-09-29

    Applicant: INTEL CORPORATION

    Inventor： Ashok Raj ,  Sivakumar Radhakrishnan ,  Dan J. Williams ,  Vishal Verma ,  Narayan Ranganathan ,  Chet R. Douglas

    IPC: G06F12/00 ,  G06F12/10 ,  G06F3/06

    Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

    COMPUTING SYSTEM WITH PROTECTION AGAINST MEMORY WEAR OUT ATTACKS
    7.
    发明申请
    COMPUTING SYSTEM WITH PROTECTION AGAINST MEMORY WEAR OUT ATTACKS 审中-公开

    公开(公告)号：US20180285562A1

    公开(公告)日：2018-10-04

    申请号：US15476196

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Sivakumar Radhakrishnan ,  Mahesh S. Natu ,  Pawel Szymanski ,  Zhenyu Zhu ,  Malay Trivedi ,  Kirk D. Brannock ,  Geoffrey S. Strongin

    IPC: G06F21/55 ,  G11C16/34 ,  G11C16/16 ,  G06F3/06

    Abstract: Technology for a computing system is described. The computing system can include memory, a controller, and a security management module. The controller can receive a block erase command for erasing data stored in a block of memory. The controller can store information associated with the block erase command in a store, wherein the information includes a block address associated with the data to be erased based on the block erase command. The security management module can read block addresses from the store, update a block erase count array over a defined interval to include block addresses read from the store, compare the block erase count array to a defined threshold, identify block addresses for which the block erase count array is above the defined threshold, and deny subsequent block erase commands for the identified block addresses.

    Enhanced cyclical redundancy check circuit based on galois-field arithmetic
    8.
    发明授权
    Enhanced cyclical redundancy check circuit based on galois-field arithmetic 有权

    公开(公告)号：US09935653B2

    公开(公告)日：2018-04-03

    申请号：US14980201

    申请日：2015-12-28

    Applicant: Intel Corporation

    Inventor： Sivakumar Radhakrishnan ,  Sin S. Tan ,  Kenneth C. Haren ,  Mark A. Schmisseur

    IPC: H03M13/07 ,  H03M13/09

    CPC classification number: H03M13/091

    Abstract: Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.

    ENHANCED CYCLICAL REDUNDANCY CHECK CIRCUIT BASED ON GALOIS-FIELD ARITHMETIC
    9.
    发明申请
    ENHANCED CYCLICAL REDUNDANCY CHECK CIRCUIT BASED ON GALOIS-FIELD ARITHMETIC 有权

    公开(公告)号：US20170187389A1

    公开(公告)日：2017-06-29

    申请号：US14980201

    申请日：2015-12-28

    Applicant: Intel Corporation

    Inventor： Sivakumar Radhakrishnan ,  Sin S. Tan ,  Kenneth C. Haren ,  Mark A. Schmisseur

    IPC: H03M13/07 ,  H03M13/09

    CPC classification number: H03M13/091

    Abstract: Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.

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