公开(公告)号：US20250006721A1

公开(公告)日：2025-01-02

申请号：US18215514

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Douglas Stout ,  Tai-Hsuan Wu ,  Xinning Wang ,  Ruth Brain ,  Chin-Hsuan Chen ,  Sivakumar Venkataraman ,  Quan Shi ,  Nikolay Ryzhenko Vladimirovich

IPC: H01L27/02 ,  G06F30/392 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.