公开(公告)号：US09697887B2

公开(公告)日：2017-07-04

申请号：US14884451

申请日：2015-10-15

Applicant: Intel Corporation

Inventor： Hieu T. Ngo ,  Daniel J. Cummings

IPC: G11C7/00 ,  G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C7/12 ,  G06F17/50 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/419 ,  G06F17/5072 ,  G11C5/066 ,  G11C5/14 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/413

Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.

公开(公告)号：US20220027792A1

公开(公告)日：2022-01-27

申请号：US17497736

申请日：2021-10-08

Applicant: Intel Corporation

Inventor： Daniel J. Cummings ,  Sharath Nittur Sridhar

IPC: G06N20/00

Abstract: The present disclosure is related to artificial intelligence (AI), machine learning (ML), and Neural Architecture Search (NAS) technologies, and in particular, to Deep Neural Network (DNN) model engineering techniques that use proxy evaluation feedback. The DNN model engineering techniques discussed herein provide near real-time feedback on model performance via low-cost proxy scores without requiring continual training and/or validation cycles, iterations, epochs, etc. In conjunction with the proxy-based scoring, semi-supervised learning mechanisms are used to map proxy scores to various model performance metrics. Other embodiments may be described and/or claimed.

公开(公告)号：US09934844B2

公开(公告)日：2018-04-03

申请号：US15396341

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Hieu T. Ngo ,  Daniel J. Cummings

IPC: G11C5/14 ,  G11C11/419 ,  G11C5/06 ,  G11C7/12 ,  G06F17/50 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/413

CPC classification number: G11C11/419 ,  G06F17/5072 ,  G11C5/066 ,  G11C5/14 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/413

Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.

公开(公告)号：US20220036123A1

公开(公告)日：2022-02-03

申请号：US17506161

申请日：2021-10-20

Applicant: Intel Corporation

Inventor： Daniel J. Cummings ,  Juan Pablo Munoz ,  Souvik Kundu ,  Sharath Nittur Sridhar ,  Maciej Szankin

IPC: G06K9/62 ,  G06N20/00

Abstract: The present disclosure is related to machine learning model swap (MLMS) framework for that selects and interchanges machine learning (ML) models in an energy and communication efficient way while adapting the ML models to real time changes in system constraints. The MLMS framework includes an ML model search strategy that can flexibly adapt ML models for a wide variety of compute system and/or environmental changes. Energy and communication efficiency is achieved by using a similarity-based ML model selection process, which selects a replacement ML model that has the most overlap in pre-trained parameters from a currently deployed ML model to minimize memory write operation overhead. Other embodiments may be described and/or claimed.

公开(公告)号：US10032507B2

公开(公告)日：2018-07-24

申请号：US15396339

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Hieu T. Ngo ,  Daniel J. Cummings

IPC: G11C11/40 ,  G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C7/12 ,  G06F17/50 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/413

Abstract: Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.