公开(公告)号：US10725920B2

公开(公告)日：2020-07-28

申请号：US15947831

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US10073779B2

公开(公告)日：2018-09-11

申请号：US13729579

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20180225211A1

公开(公告)日：2018-08-09

申请号：US15947829

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. HUM ,  Brinda GANESH ,  James R. VASH ,  Ganesh KUMAR ,  Leena K. PUTHIYEDATH ,  Scott J. ERLANGER ,  Eric J. DEHAEMER ,  Adrian C. MOGA ,  Michelle M. SEBOT ,  Richard L. CARLSON ,  David Bubien ,  Eric Delano

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US10725919B2

公开(公告)日：2020-07-28

申请号：US15947829

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US10705960B2

公开(公告)日：2020-07-07

申请号：US15947830

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric DeLano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.