公开(公告)号：US20250123848A1

公开(公告)日：2025-04-17

申请号：US18634236

申请日：2024-04-12

Applicant: Intel Corporation

Inventor： Yi-Feng LIU ,  Eric J. DEHAEMER ,  Eswaramoorthi NALLUSAMY

IPC: G06F9/4401 ,  G06F9/54

Abstract: Examples described herein relate to partitioning of processor sockets. A first processor socket includes first communication circuitry associated with a first partition identifier and a second processor socket includes a second communication circuitry associated with a second partition identifier. In some examples, based on a boot operation associated with the first processor socket: the first communication circuitry is to permit communication with the second communication circuitry based on a first partition identifier matching the second partition identifier and the first communication circuitry is to disable communication with the second communication circuitry based on the first partition identifier not matching the second partition identifier.

公开(公告)号：US20180225213A1

公开(公告)日：2018-08-09

申请号：US15947831

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. HUM ,  Brinda GANESH ,  James R. VASH ,  Ganesh KUMAR ,  Leena K. PUTHIYEDATH ,  Scott J. ERLANGER ,  Eric J. DEHAEMER ,  Adrian C. MOGA ,  Michelle M. SEBOT ,  Richard L. CARLSON ,  David BUBIEN ,  Eric DELANO

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20180225212A1

公开(公告)日：2018-08-09

申请号：US15947830

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. HUM ,  Brinda GANESH ,  James R. VASH ,  Ganesh KUMAR ,  Leena K. PUTHIYEDATH ,  Scott J. ERLANGER ,  Eric J. DEHAEMER ,  Adrian C. MOGA ,  Michelle M. SEBOT ,  Richard L. CARLSON ,  David BUBIEN ,  Eric DELANO

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20240272911A1

公开(公告)日：2024-08-15

申请号：US18645295

申请日：2024-04-24

Applicant: Intel Corporation

Inventor： Ramamurthy KRITHIVAS ,  Eswaramoorthi NALLUSAMY ,  Anand K. ENAMANDRAM ,  Mahesh S. NATU ,  Eric J. DEHAEMER ,  Filip SCHMOLE ,  Bharat S. PILLILLI

IPC: G06F9/4401

CPC classification number: G06F9/4403

Abstract: Examples described herein relate to an apparatus that includes an interface and circuitry to: prior to boot of a processor, configure a memory address decoder to increase a memory region size associated with firmware access from a first size to a second size, wherein the second size is larger than the first size. In some examples, the memory address decoder is to decode an address space in a Serial Peripheral Interface (SPI) flash device to determine a location of a Firmware Interface Table (FIT) in the second size of the memory region and the second circuitry is to access an entry in the FIT to determine a location of a boot firmware.

公开(公告)号：US20210191490A1

公开(公告)日：2021-06-24

申请号：US17191564

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Phani Kumar KANDULA ,  Eric J. DEHAEMER ,  Dorit SHAPIRA ,  Ramkumar NAGAPPAN ,  Vivek GARG ,  Fuat KECELI ,  Mani PRAKASH ,  David C. HOLCOMB ,  Horthense D. TAMDEM ,  Olivier FRANZA ,  Vjekoslav SVILAN

IPC: G06F1/324

Abstract: Methods and apparatus for balancing power between discrete components, such as processing units (e.g., CPUs) and accelerators in a compute node or platform. Power consumption of the compute platform is monitored to detect for conditions under which a threshold (e.g., power supply capacity threshold) is exceeded. In response, the operating frequencies of a processing unit and/or other platform components such as accelerators, are adjusted to reduce the power consumption of the platform to return below the threshold. Power limit biasing hints (scaling weights) are provided to platform components, along with a power violation index, which are used to adjust the operating frequencies of the platform components. Optionally, a processing unit can calculate the power violation index and the scaling weights and directly control the frequencies of itself and platform components. Embodiments of multi-socket platforms are also provided.

公开(公告)号：US20180225211A1

公开(公告)日：2018-08-09

申请号：US15947829

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. HUM ,  Brinda GANESH ,  James R. VASH ,  Ganesh KUMAR ,  Leena K. PUTHIYEDATH ,  Scott J. ERLANGER ,  Eric J. DEHAEMER ,  Adrian C. MOGA ,  Michelle M. SEBOT ,  Richard L. CARLSON ,  David Bubien ,  Eric Delano

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.