公开(公告)号：US10725920B2

公开(公告)日：2020-07-28

申请号：US15947831

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US09207753B2

公开(公告)日：2015-12-08

申请号：US14519584

申请日：2014-10-21

Applicant: Intel Corporation

Inventor： James R. Vash ,  Pritpal S. Ahuja ,  Bongjin Jung ,  Jeffrey D. Chamberlain

IPC: G06F1/32 ,  G06F13/00 ,  G06F13/16 ,  H04L29/00

CPC classification number: G06F1/3293 ,  G06F13/00 ,  G06F13/1642 ,  H04L29/00 ,  Y02D10/14

Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.

Abstract translation: 描述了在基于重试的流水线中与多队列多资源进入睡眠和唤醒功率节省和带宽保持有关的方法和装置。 在一个实施例中，一位指示相应的队列条目是否相对于基于重试的流水线中的资源的仲裁而睡眠或唤醒。 此外，来自不同队列的多个条目可以被分组在一起，并且多个资源可以被分组在一起。 还公开了其他实施例。

公开(公告)号：US10725919B2

公开(公告)日：2020-07-28

申请号：US15947829

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US10705960B2

公开(公告)日：2020-07-07

申请号：US15947830

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric DeLano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20150160720A1

公开(公告)日：2015-06-11

申请号：US14519584

申请日：2014-10-21

Applicant: Intel Corporation

Inventor： James R. Vash ,  Pritpal S. Ahuja ,  Bongjin Jung ,  Jeffrey D. Chamberlain

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  G06F13/00 ,  G06F13/1642 ,  H04L29/00 ,  Y02D10/14

Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.

Abstract translation: 描述了在基于重试的流水线中与多队列多资源进入睡眠和唤醒功率节省和带宽保持有关的方法和装置。 在一个实施例中，一位指示相应的队列条目是否相对于基于重试的流水线中的资源的仲裁而睡眠或唤醒。 此外，来自不同队列的多个条目可以被分组在一起，并且多个资源可以被分组在一起。 还公开了其他实施例。

公开(公告)号：US10073779B2

公开(公告)日：2018-09-11

申请号：US13729579

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US09304922B2

公开(公告)日：2016-04-05

申请号：US14307019

申请日：2014-06-17

Applicant: Intel Corporation

Inventor： James R. Vash ,  Bongjin Jung ,  Pritpal S. Ahuja

IPC: G06F13/38 ,  G06F12/08 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F12/0815 ,  G06F13/1642 ,  G06F2212/621

Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.

Abstract translation: 描述了在基于重试的管道中与具有动态死锁避免的队列间抗饥饿机制有关的方法和装置。 在一个实施例中，逻辑可以基于各种规则在两个队列之间仲裁。 队列可以存储包括本地或远程请求，数据响应，非数据响应，外部中断等的数据。还公开了其他实施例。

公开(公告)号：US09288260B2

公开(公告)日：2016-03-15

申请号：US14048254

申请日：2013-10-08

Applicant: Intel Corporation

Inventor： James R. Vash ,  Vida Vakilotojar ,  Bongjin Jung ,  Yen-Cheng Liu

IPC: G06F15/16 ,  H04L29/08 ,  G06F15/173

CPC classification number: H04L67/10 ,  G06F15/17325

Abstract: Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.