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    Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric
    1.
    发明授权
    Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric 有权

    公开(公告)号：US10133670B2

    公开(公告)日：2018-11-20

    申请号：US14583611

    申请日：2014-12-27

    Applicant: Intel Corporation

    Inventor： Ramadass Nagarajan ,  Jose S. Niell ,  Michael T. Klinglesmith ,  Derek T. Bachand ,  Ganesh Kumar

    IPC: G06F12/0815 ,  G06F13/28 ,  G06F13/42

    Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.

    LOW OVERHEAD HIERARCHICAL CONNECTIVITY OF CACHE COHERENT AGENTS TO A COHERENT FABRIC
    4.
    发明申请
    LOW OVERHEAD HIERARCHICAL CONNECTIVITY OF CACHE COHERENT AGENTS TO A COHERENT FABRIC 审中-公开
    高速缓存代码对相邻纸张的低层叠层连接性

    公开(公告)号：US20160188469A1

    公开(公告)日：2016-06-30

    申请号：US14583611

    申请日：2014-12-27

    Applicant: Intel Corporation

    Inventor： Ramadass Nagarajan ,  Jose S. Niell ,  Michael T. Klinglesmith ,  Derek T. Bachand ,  Ganesh Kumar

    IPC: G06F12/08 ,  G06F13/42 ,  G06F13/28

    CPC classification number: G06F12/0815 ,  G06F9/5016 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/287 ,  G06F13/4282 ,  G06F2212/1028 ,  G06F2212/154 ,  G06F2212/621

    Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.

    Abstract translation: 在一个示例中，片上系统包括多个多核处理器，例如用于八个总核的四个双核处理器。 每个处理器通过共享的无孔结构连接到诸如存储器和外围设备之类的共享资源。 因为每个核心的每个输入总线可以包含数百条数据线，所以共享的非空心结构中的行数可能变得过高。 因此，来自每个核的输入被复用，例如以二对一的配置。 多路复用可以是非阻塞排队（例如FIFO）复用，以确保来自所有核心的所有分组被传送到非空心结构。 在某些实施例中，可以向未多路复用的非空心结构提供一些较小的输入线，并且还可以将从非织造结构返回（输出）到芯的非多路复用。

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