公开(公告)号：US20220308867A1

公开(公告)日：2022-09-29

申请号：US17214572

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Tyler SONDAG ,  David SHEFFIELD ,  Sofia PEDIADITAKI

IPC: G06F9/22 ,  G06F9/455

Abstract: An apparatus and method for supporting deprecated instructions. For example, one embodiment of a processor comprises: A processor comprising: a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; at least one core of the plurality of cores comprising: a decoder to decode the instructions, the decoder to specify one or more microoperations corresponding to each of the instructions; execution circuitry to execute the corresponding microoperations; wherein either a first type or a second type of virtual machine exit is to be performed responsive to detecting a deprecated instruction in a first virtual machine, wherein responsive to the first type of virtual machine exit, the hypervisor is to perform a first emulation of the prior microarchitecture without reliance on the partial hardware support, and wherein responsive to the second type of virtual machine exit, the hypervisor is to perform a second emulation of the prior microarchitecture relying on the partial hardware support.

公开(公告)号：US20240143361A1

公开(公告)日：2024-05-02

申请号：US17958336

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Tyler SONDAG ,  Andreas KLEEN ,  David SHEFFIELD ,  Xiang ZOU ,  Terry PARKS ,  Jason BRANDT ,  Ittai ANATI

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/45558 ,  G06F9/3016 ,  G06F9/3802 ,  G06F2009/45591

Abstract: An apparatus and method for implementing a new virtualized execution environment while supporting instructions and operations of a legacy virtualized execution environment. For example, one embodiment of a processor comprises: instruction processing circuitry to process instructions in accordance with a microarchitecture, the instruction processing circuitry comprising: instruction fetch circuitry to fetch the instructions; a decoder to decode the instructions; and execution circuitry to execute the instructions based on the microarchitecture; wherein the microarchitecture including hardware support for a virtual execution environment including a virtual machine monitor (VMM) and a first type of virtual machine, wherein both the VMM and the first type of virtual machine are implemented by instructions directly supported by the microarchitecture; and wherein the VMM is to support a second type of virtual machine, the second type of virtual machine including legacy instructions not fully supported by the microarchitecture, the VMM comprising a plurality of emulators, each emulator configured to emulate execution of a different type of the legacy instructions.

公开(公告)号：US20240320341A1

公开(公告)日：2024-09-26

申请号：US18217361

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Andreas KLEEN ,  David SHEFFIELD ,  Xiang ZOU ,  Jason BRANDT

IPC: G06F21/57 ,  G06F9/30

CPC classification number: G06F21/575 ,  G06F9/30098

Abstract: An apparatus and method for booting a processor directly into a paged 64-bit execution environment. For example, one embodiment of an a processor comprises: a register to store a first value and a second value related to a secure boot process; a plurality of cores, at least one of which performs operations comprising: receiving a first initialization message, the core to clear a plurality of registers responsively; receiving a second initialization message and reading the first and second values responsively, the first value indicating whether a first initialization mode is supported, and the second value comprising an address pointer identifying a data structure comprising a plurality of state values; and initializing a paged 64-bit execution environment using the state values from the data structure responsive to the first value indicating the first initialization mode is supported and the data structure indicating enabling the paged 64-bit execution environment.

公开(公告)号：US20240320002A1

公开(公告)日：2024-09-26

申请号：US18375381

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Jay LAWLOR ,  David SHEFFIELD ,  Xiang ZOU ,  Michael KINNEY ,  Charles HOLTHAUS ,  Thomas TOLL ,  Salessawi Ferede YITBAREK ,  Andreas KLEEN ,  Keshavan TIRUVALLUR ,  Sarathy JAYAKUMAR ,  Ruiyu NI

IPC: G06F9/30 ,  G06F9/48 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F9/30043 ,  G06F9/4812 ,  G06F12/0238 ,  G06F12/1009

Abstract: An apparatus and method for a more efficient system management mode. For example, one embodiment of a processor comprises: a plurality of cores, at least a first core of the plurality of cores to perform operations to cause the plurality of cores to enter into a system management mode (SMM), the operations comprising: allocating a memory region for a system management RAM (SMRAM); writing an SMRAM state save location to a first register; and generating a page table in the SMRAM, including mapping a virtual address space a physical address space.

公开(公告)号：US20240143513A1

公开(公告)日：2024-05-02

申请号：US17958337

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Gilbert NEIGER ,  Andreas KLEEN ,  David SHEFFIELD ,  Jason BRANDT ,  Ittai ANATI ,  Vedvyas SHANBHOGUE ,  Ido OUZIEL ,  Michael S. BAIR ,  Barry E. HUNTLEY ,  Joseph NUZMAN ,  Toby OPFERMAN ,  Michael A. ROTHMAN

IPC: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

Abstract: An apparatus and method for switching between different types of paging using separate control registers and without disabling paging. For example, one embodiment of a processor comprises: a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels; a second control register to store a second base address of a second paging structure associated with a first type of paging having a second number of paging structure levels greater than the first number of paging structure levels; page walk circuitry to select either the first base address from the first control register or the second base address from the second control register responsive to a first address translation request, the selection based on a characteristic of program code initiating the address translation request.