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公开(公告)号:US20230315460A1
公开(公告)日:2023-10-05
申请号:US17712129
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/3009 , G06F9/30094
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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公开(公告)号:US20230315455A1
公开(公告)日:2023-10-05
申请号:US17712118
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3009 , G06F9/30105 , G06F9/30043 , G06F9/30047
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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公开(公告)号:US20230315572A1
公开(公告)日:2023-10-05
申请号:US17712121
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
CPC classification number: G06F11/1405 , G06F9/3861 , G06F15/7889 , G06F9/3009 , G06F9/226
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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公开(公告)号:US20230315459A1
公开(公告)日:2023-10-05
申请号:US17712122
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/3009 , G06F9/3013
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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公开(公告)号:US20230315445A1
公开(公告)日:2023-10-05
申请号:US17712126
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
CPC classification number: G06F9/223 , G06F9/30101 , G06F9/3009
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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公开(公告)号:US20220308867A1
公开(公告)日:2022-09-29
申请号:US17214572
申请日:2021-03-26
Applicant: Intel Corporation
Inventor: Tyler SONDAG , David SHEFFIELD , Sofia PEDIADITAKI
Abstract: An apparatus and method for supporting deprecated instructions. For example, one embodiment of a processor comprises: A processor comprising: a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; at least one core of the plurality of cores comprising: a decoder to decode the instructions, the decoder to specify one or more microoperations corresponding to each of the instructions; execution circuitry to execute the corresponding microoperations; wherein either a first type or a second type of virtual machine exit is to be performed responsive to detecting a deprecated instruction in a first virtual machine, wherein responsive to the first type of virtual machine exit, the hypervisor is to perform a first emulation of the prior microarchitecture without reliance on the partial hardware support, and wherein responsive to the second type of virtual machine exit, the hypervisor is to perform a second emulation of the prior microarchitecture relying on the partial hardware support.
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7.
公开(公告)号:US20240143361A1
公开(公告)日:2024-05-02
申请号:US17958336
申请日:2022-10-01
Applicant: Intel Corporation
Inventor: Tyler SONDAG , Andreas KLEEN , David SHEFFIELD , Xiang ZOU , Terry PARKS , Jason BRANDT , Ittai ANATI
CPC classification number: G06F9/45558 , G06F9/3016 , G06F9/3802 , G06F2009/45591
Abstract: An apparatus and method for implementing a new virtualized execution environment while supporting instructions and operations of a legacy virtualized execution environment. For example, one embodiment of a processor comprises: instruction processing circuitry to process instructions in accordance with a microarchitecture, the instruction processing circuitry comprising: instruction fetch circuitry to fetch the instructions; a decoder to decode the instructions; and execution circuitry to execute the instructions based on the microarchitecture; wherein the microarchitecture including hardware support for a virtual execution environment including a virtual machine monitor (VMM) and a first type of virtual machine, wherein both the VMM and the first type of virtual machine are implemented by instructions directly supported by the microarchitecture; and wherein the VMM is to support a second type of virtual machine, the second type of virtual machine including legacy instructions not fully supported by the microarchitecture, the VMM comprising a plurality of emulators, each emulator configured to emulate execution of a different type of the legacy instructions.
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公开(公告)号:US20230315462A1
公开(公告)日:2023-10-05
申请号:US17712127
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
CPC classification number: G06F9/3017 , G06F9/223 , G06F9/3009
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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公开(公告)号:US20230315461A1
公开(公告)日:2023-10-05
申请号:US17712130
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/3009
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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公开(公告)号:US20230315444A1
公开(公告)日:2023-10-05
申请号:US17712124
申请日:2022-04-02
Applicant: Intel Corporation
Inventor: David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
CPC classification number: G06F9/223 , G06F9/3017 , G06F9/30101
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
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