公开(公告)号：US10936507B2

公开(公告)日：2021-03-02

申请号：US16367592

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Esha Choukse ,  Shankar Ganesh Ramasubramanian ,  Melin Dadual ,  Suresh Chittor

IPC: G06F12/10 ,  G06F12/1009 ,  G06F16/907 ,  G06F9/54 ,  G06F12/0873 ,  G06F9/4401

Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

公开(公告)号：US20200310979A1

公开(公告)日：2020-10-01

申请号：US16367592

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Esha Choukse ,  Shankar Ganesh Ramasubramanian ,  Melin Dadual ,  Suresh Chittor

IPC: G06F12/1009 ,  G06F12/0873 ,  G06F16/907 ,  G06F9/54

Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.

公开(公告)号：US11216386B2

公开(公告)日：2022-01-04

申请号：US16584612

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Suresh Chittor ,  Esha Choukse ,  Shankar Ganesh Ramasubramanian

IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/06 ,  G06F11/30 ,  G06F13/16 ,  G06F12/02

Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.