公开(公告)号：US20220004500A1

公开(公告)日：2022-01-06

申请号：US17479702

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Francois Dugast ,  Neha Pathapati ,  Durgesh Srivastava

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/0831

Abstract: An apparatus of a computing system, the computing system, a method to be performed at the apparatus, and a machine-readable storage medium. The apparatus includes control circuitry to: perform a page walk operation on a page table structure of a pooled memory; based on the page walk operation, determine page table entries (PTEs) corresponding to a workload to be executed by the computing system; and during a time interval not including a page walk operation by the control circuitry, perform a plurality of sampling operations, individual ones of the sampling operations including determining PTE metadata corresponding to at least some of the PTEs.

公开(公告)号：US20220012209A1

公开(公告)日：2022-01-13

申请号：US17485203

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Francois Dugast ,  Neha Pathapati ,  Durgesh Srivastava

IPC: G06F16/16

Abstract: An apparatus of a computing system, the computing system, a method to be performed at the apparatus, and a machine-readable storage medium. The apparatus includes control circuitry to: perform a page walk operation on a page table structure of a pooled memory; based on the page walk operation, determine page table entries (PTEs) corresponding to a workload to be executed by the computing system; and during a time interval not including a page walk operation by the control circuitry, perform a plurality of sampling operations, individual ones of the sampling operations including determining PTE metadata corresponding to at least some of the PTEs.

公开(公告)号：US12086446B2

公开(公告)日：2024-09-10

申请号：US17031721

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Thomas E. Willis ,  Durgesh Srivastava ,  Marcelo Cintra ,  Bassam N. Coury ,  Donald L. Faw ,  Francois Dugast

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067

Abstract: Examples herein relate to a system capable of coupling to a remote memory pool, the system comprising: a memory controller and an interface to a connection, the interface coupled to the memory controller. In some examples, the interface is to translate a format of a memory access request to a format accepted by the memory controller and the memory controller is to provide the translated memory access request in a format accepted by a media. In some examples, a controller is to measure a number of addressable regions that are least accessed and cause at least one of the least accessed regions to be evicted to a local or remote memory device with relatively higher latency. In some examples, a remote access manager is to: determine if a region of addressable memory associated with a memory address for an access request is stored in the memory; based on the region of addressable memory associated with the memory address being stored in the memory, determine if a sub-region of addressable memory associated with the memory address is available for access from the memory, wherein the sub-region comprises less than an entirety of the region; and based on the sub-region of addressable memory being available for access from the memory, provide a physical address for use to access data from the sub-region in the memory and copy the data to the cache.

公开(公告)号：US20210377150A1

公开(公告)日：2021-12-02

申请号：US17404736

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Francois Dugast ,  Francesc Guim Bernat ,  Durgesh Srivastava ,  Karthik Kumar

IPC: H04L12/727 ,  H04L12/729 ,  H04L12/721 ,  H04L12/741 ,  H04L12/26

Abstract: A system comprising a traffic handler comprising circuitry to determine that data of a memory request is stored remotely in a memory pool; generate a packet based on the memory request; and direct the packet to a path providing a guaranteed latency for completion of the memory request.