公开(公告)号：US10990146B2

公开(公告)日：2021-04-27

申请号：US16359810

申请日：2019-03-20

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Pradipta Patra ,  Gaurav Goel ,  Uday Bhaskar Kadali

IPC: G06F1/00 ,  G06F1/26 ,  G05F1/59

Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.

公开(公告)号：US10268249B2

公开(公告)日：2019-04-23

申请号：US15025871

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Ramnarayanan Muthukaruppan ,  Pradipta Patra ,  Gaurav Goel ,  Uday Bhaskar Kadali

IPC: G06F1/26 ,  G05F1/59

Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.

公开(公告)号：US11016550B2

公开(公告)日：2021-05-25

申请号：US16062093

申请日：2016-11-23

Applicant: INTEL CORPORATION

Inventor： Ramnarayanan Muthukaruppan ,  Anoop Kumar Upadhyay ,  Gaurav Goel ,  Amit Kumar Srivastava

IPC: G06F1/24 ,  G06F9/00 ,  G06F1/28 ,  G06F1/3287 ,  G06F13/40 ,  G06F1/3234 ,  G06F9/445 ,  G06F13/20

Abstract: A configuration interface bus may be coupled to components of a physical layer (PHY) device. A configuration controller may be coupled with the configuration interface bus and may receive an input signal representing a power state of the PHY device. The configuration controller may further identify a set of instructions that correspond to the input signal and may transmit configuration data via the configuration interface bus to one or more of the components of the PHY device in response to an execution of the set of instructions. The operation of the one or more components of the PHY device may be based on the configuration data.