公开(公告)号：US20230185624A1

公开(公告)日：2023-06-15

申请号：US17952120

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Le Yao ,  Ruijing Guo ,  Malini K. Bhandaru ,  Qiaowei Ren ,  Haibin Huang ,  Ruoyu Ying

IPC: G06F9/50 ,  G06F9/54

CPC classification number: G06F9/505 ,  G06F9/54

Abstract: A processing circuitry, a method to be performed at the processing circuitry, a computer-readable storage medium, and a computing system. The processing circuitry is to determine a first mapping between a first set of data parameters and first computing units of a computing network; select, based on the first mapping and on first data having a first workload associated therewith, one or more of the first computing units to execute the first workload, and send for execution the first workload to the one or more of the first computing units; determine a second mapping based on a change in computing units from the first computing units to second computing units, the second mapping between a second set of data parameters and the second computing units; and select, based on the second mapping and on second data having a second workload associated therewith, one or more of the second computing units to execute the second workload.

公开(公告)号：US20220357975A1

公开(公告)日：2022-11-10

申请号：US17868408

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Haibin Huang ,  Xinyu Huang ,  Qiaowei Ren ,  Ruoyu Ying

IPC: G06F9/455

Abstract: In one embodiment, a request is sent to an image registry for at least one virtual environment image block of an image for a virtual environment. The at least one virtual environment image block is processed upon reception of the at least one virtual environment image block from the image registry. The processed at least one virtual environment image block is communicated to a worker node that is to execute the virtual environment.

公开(公告)号：US20230188341A1

公开(公告)日：2023-06-15

申请号：US18106259

申请日：2023-02-06

Applicant: Intel Corporation

Inventor： Ruoyu Ying ,  Ruijing Guo ,  Shaojun Ding ,  Qiang Ren ,  Haibin Huang ,  Jie Ren

IPC: H04L9/08 ,  G06F21/53

CPC classification number: H04L9/0897 ,  G06F21/53

Abstract: An apparatus can include an interface coupled to processing circuitry and cryptographic circuitry coupled to the interface. The cryptographic circuitry can receive a request from the processing circuitry over the interface to perform a cryptographic operation using a remote hardware security module (HSM) key component. The cryptographic circuitry can further transmit a command to a remote component to retrieve the remote HSM key component. Subsequent to receiving the cryptographic key component, the cryptographic circuitry can construct a trusted execution environment (TEE) instance and store the remote HSM key component in the TEE instance. The cryptographic circuitry can use the remote HSM key component to perform the cryptographic operation and provide a result of the cryptographic operation to the processing circuitry over the interface.