公开(公告)号：US20190393165A1

公开(公告)日：2019-12-26

申请号：US16481031

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Jaejin LEE ,  Hao-Han HSU ,  Chung-Hao J. CHEN ,  Dong-Ho HAN

IPC: H01L23/552 ,  H01L23/498 ,  H01L25/18 ,  H05K1/18 ,  H01L21/48

Abstract: Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer, a conductive layer formed in the foundation layer, and a magnetic layer formed between the conductive and the foundation layer. The conductive layer and the magnetic layer are coupled to form a low-profile inductor shield. The semiconductor package also has a dielectric layer formed between the magnetic and foundation layer. The foundation layer is mounted between a motherboard and a semiconductor die, where the foundation layer is attached to the motherboard with solder balls. Accordingly, the low-profile inductor shield may include a z-height that is less than a z-height of the solder balls. The low-profile inductor shield may have solder pads that are coupled to the conductive layer. The foundation layer may include at least one of voltage regulator and inductor, where the inductor is located above the low-profile inductor shield.

公开(公告)号：US20200066658A1

公开(公告)日：2020-02-27

申请号：US16326084

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Hao-Han HSU ,  Dong-Ho HAN ,  Steven C. WACHTMAN ,  Ryan K. KUHLMANN

IPC: H01L23/64 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01P1/20

Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.

公开(公告)号：US20230074049A1

公开(公告)日：2023-03-09

申请号：US17987782

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Yingern HO ,  Hao-Han HSU ,  Boon Ping KOH

IPC: H04L25/03 ,  H04L25/02

Abstract: Differential signal skew compensation techniques for radio frequency interference (RFI) mitigation with no reflection penalty and associated apparatus and methods. A differential pair of signal traces are formed on or in a PCB having at least two changes in direction, with a first signal trace having a first routing path defining a first length and a second signal trace adjacent to the first signal trace including one or more tuning structures that are configured such that the length of the second signal trace matches the first length. Segments of the first signal trace adjacent to the one or more tuning structures of the second signal trace are widened relative to other segments of the first signal trace. The tuning structures may comprise sawtooth structures, accordion structures and other serpentine or meander structures. The solution mitigates RFI without a reflection penalty.

公开(公告)号：US20210193598A1

公开(公告)日：2021-06-24

申请号：US17194006

申请日：2021-03-05

Applicant: Intel Corporation

Inventor： Hao-Han HSU ,  Dong-Ho HAN ,  Steven C. WACHTMAN ,  Ryan K. KUHLMANN

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01P1/20

Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.