公开(公告)号：US20230317706A1

公开(公告)日：2023-10-05

申请号：US17710753

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Kuang LIU ,  Bohan SHAN ,  Hongxia FENG ,  Don Douglas JOSEPHSON ,  Stephen MOREIN ,  Kaladhar RADHAKRISHNAN

IPC: H01L25/18 ,  H01L23/373 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L23/3736 ,  H01L25/0652 ,  H01L24/40 ,  H01L23/538 ,  H01L21/4871 ,  H01L24/37 ,  H01L2224/37147 ,  H01L24/83 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L24/33 ,  H01L2224/3303 ,  H01L24/06 ,  H01L2224/0603 ,  H01L2224/32258 ,  H01L2224/4046 ,  H01L24/32 ,  H01L2224/40499 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

公开(公告)号：US20220094256A1

公开(公告)日：2022-03-24

申请号：US17025745

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Beomseok CHOI ,  Michael HILL

IPC: H02M1/00 ,  H02M3/07

Abstract: Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.

公开(公告)号：US20210327795A1

公开(公告)日：2021-10-21

申请号：US17360701

申请日：2021-06-28

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Kaladhar RADHAKRISHNAN ,  Kemal AYGUN

IPC: H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20230307441A1

公开(公告)日：2023-09-28

申请号：US17706454

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Ahmed ABOU-ALFOTOUH ,  Jonathan DOUGLAS ,  Alan WU ,  Nachiket Venkappayya DESAI ,  Han Wui THEN ,  Harish KRISHNAMURTHY ,  Kaladhar RADHAKRISHNAN ,  Sanka GANESAN ,  Krishnan RAVICHANDRAN

IPC: H01L27/06 ,  H05K1/18 ,  H01F27/28 ,  H01F27/24 ,  H01F27/40 ,  H01L49/02 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L27/0605 ,  H05K1/181 ,  H01F27/28 ,  H01F27/24 ,  H01F27/40 ,  H01L28/10 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786 ,  H05K2201/1003 ,  H05K2201/10734

Abstract: Embodiments disclosed herein include a coupled inductor. In an embodiment, the coupled inductor comprises a first inductor and a second inductor. In an embodiment, the first inductor can be coupled to the first inductor. In an embodiment, the coupled inductor further comprises a first switch coupled to the first inductor, where the first switch comprises gallium and nitrogen, and a second switch coupled to the second inductor, where the second switch comprises gallium and nitrogen.

公开(公告)号：US20230089093A1

公开(公告)日：2023-03-23

申请号：US17482804

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Krishna BHARATH ,  Bharat PENMECHA ,  Anderw COLLINS ,  Kaladhar RADHAKRISHNAN ,  Sriram SRINIVASAN

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a plug is formed through the core, where the plug comprises a magnetic material. In an embodiment, an inductor is around the plug. In an embodiment, first layers are over the core, wherein where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.

公开(公告)号：US20200013533A1

公开(公告)日：2020-01-09

申请号：US16026401

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Malavarayan SANKARASUBRAMANIAN ,  Anne AUGUSTINE ,  Yongki MIN ,  Kaladhar RADHAKRISHNAN

IPC: H01F17/04 ,  H01L23/00 ,  H01F27/28

Abstract: A microelectronics package, comprising a substrate that comprises a dielectric and an inductor component comprising one or more wires within a magnetic core over the dielectric. The inductor component is bonded to the substrate by one or more solder joints. A solder mask is between the inductor component and the dielectric. The one or more solder joints are surrounded by the solder mask, and wherein the solder mask comprises a magnetic material.

公开(公告)号：US20230189442A1

公开(公告)日：2023-06-15

申请号：US18015702

申请日：2020-09-16

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Wei SHEN

IPC: H05K1/18 ,  H05K1/02 ,  H01L25/16

CPC classification number: H05K1/183 ,  H05K1/0209 ,  H01L25/162 ,  H05K1/181 ,  H05K2201/1003 ,  H05K2201/10015 ,  H05K2201/10734 ,  H01L24/16

Abstract: Embodiments disclosed herein include microelectronic boards and electronic systems. In an embodiment, a microelectronic board comprises aboard substrate, where the board substrate has a first thickness between a first surface and a second surface opposite from the first surface. In an embodiment, a recess is formed into the first surface of the board substrate, where the recess comprises a third surface between the first surface and the second surface. In an embodiment, the board substrate has a second thickness between the third surface and the second surface. In an embodiment, the microelectronic board further comprises a voltage regulator (VR) module attached to the third surface.

公开(公告)号：US20220094263A1

公开(公告)日：2022-03-24

申请号：US17030132

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Christopher SCHAEF ,  William J. LAMBERT ,  Kaladhar RADHAKRISHNAN

IPC: H02M3/04 ,  H01F27/24 ,  H01L49/02

Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

公开(公告)号：US20220093565A1

公开(公告)日：2022-03-24

申请号：US17031819

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Kaladhar RADHAKRISHNAN ,  Krishna BHARATH

IPC: H01L25/065 ,  H01L49/02 ,  H01L23/00 ,  H01L23/64

Abstract: Embodiments disclosed herein include voltage regulators VR integrated into an electronic device. In an embodiment, an electronic device comprises a package substrate, a first die electrically coupled to the package substrate, and a second die with a first surface facing the first die and second surface facing the package substrate that is electrically coupled to the package substrate and the first die. In an embodiment, the second die is between the package substrate and the first die. In an embodiment, the second die comprises voltage regulation (VR) circuitry. In an embodiment current is received by the second die through only the first surface and the current only exits the second die through the second surface.

公开(公告)号：US20200005983A1

公开(公告)日：2020-01-02

申请号：US16024718

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Malavarayan SANKARASUBRAMANIAN ,  Yongki MIN ,  Anne AUGUSTINE ,  Kaladhar RADHAKRISHNAN ,  Taylor GAINES ,  Ziyin LIN

IPC: H01F27/02 ,  H01F1/42 ,  H01F41/00 ,  H01F1/01 ,  H01L25/16 ,  H01L21/48 ,  H01F27/29

Abstract: Embodiments herein relate to a magnetic encapsulant composite, comprising a mixture of a first material that is a soft magnetic filler, a second material that is a polymer matrix, and a third material that is a process ingredient. The magnetic encapsulant composite may then encapsulate or partially encapsulate a magnetic inductor coupled to a substrate to increase the inductance of the magnetic inductor and/or to strengthen the substrate to which the magnetic inductor and the composite are coupled.