公开(公告)号：US20180088853A1

公开(公告)日：2018-03-29

申请号：US15276677

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Jagadish B. KOTRA ,  Alaa R. ALAMELDEEN ,  Christopher B. WILKERSON ,  Jaewoong SIM

IPC: G06F3/06 ,  G06F12/0842

CPC classification number: G06F12/0842 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F2212/311 ,  G06F2212/62

Abstract: A method is described. The method includes performing the following in a computing system having a multi-level system memory, the multi-level system memory having a first level and a second level: switching between utilization of the first level as a cache for the second level and separately addressable system memory depending on a state of the computing system.