公开(公告)号：US20180088853A1

公开(公告)日：2018-03-29

申请号：US15276677

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Jagadish B. KOTRA ,  Alaa R. ALAMELDEEN ,  Christopher B. WILKERSON ,  Jaewoong SIM

IPC: G06F3/06 ,  G06F12/0842

CPC classification number: G06F12/0842 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F2212/311 ,  G06F2212/62

Abstract: A method is described. The method includes performing the following in a computing system having a multi-level system memory, the multi-level system memory having a first level and a second level: switching between utilization of the first level as a cache for the second level and separately addressable system memory depending on a state of the computing system.

公开(公告)号：US20190042145A1

公开(公告)日：2019-02-07

申请号：US15854357

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Binh PHAM ,  Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zeshan A. CHISHTI ,  Zhe WANG

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/0897

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

公开(公告)号：US20180285274A1

公开(公告)日：2018-10-04

申请号：US15476838

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Elvira TERAN ,  Zeshan A. CHISHTI ,  Christopher B. WILKERSON ,  Zhe WANG

IPC: G06F12/0864 ,  G06F12/0804 ,  G06F12/0873 ,  G06F13/16 ,  G06F12/02 ,  G06F12/06

Abstract: Provided are an apparatus, method, and system for just-in-time cache associativity for a cache memory having cache locations as a cache for a non-volatile memory. Data is received for a target address in the non-volatile memory to add to the cache memory. A determination is made of a direct mapped cache location in the cache memory from the a target address in the non-volatile memory. The data for the target address at an available cache location in the cache memory different from the direct mapped cache location is written in response to the direct mapped cache location storing data for another address in the non-volatile memory. The data for the target address in the direct mapped cache location is written in response to the direct mapped cache location not storing data for another address in the non-volatile memory.

公开(公告)号：US20170277633A1

公开(公告)日：2017-09-28

申请号：US15400122

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： Christopher B. WILKERSON ,  Alaa R. ALAMELDEEN ,  Zhe WANG ,  Zeshan A. CHISHTI

IPC: G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0292 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/608 ,  G06F2212/651 ,  G11C8/00 ,  G11C11/56 ,  G11C16/08

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

公开(公告)号：US20250005100A1

公开(公告)日：2025-01-02

申请号：US18217564

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  AppaRao CHALLAGUNDLA ,  Sanu K. MATHEW ,  Christopher B. WILKERSON ,  Adish VARTAK ,  Sachin TANEJA ,  Minxuan ZHOU ,  Lalith Dharmesh KETHARESWARAN

IPC: G06F17/14

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload.

公开(公告)号：US20180189182A1

公开(公告)日：2018-07-05

申请号：US15394649

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F12/0864 ,  G06F12/0891 ,  G06F17/30

CPC classification number: G06F12/0864 ,  G06F12/0891 ,  G06F2212/1024

Abstract: In one embodiment, aggregated write back in a direct mapped two level memory in accordance with the present description, aggregates a dirty block or other subunit of data being evicted from a near memory of a two level memory system, with other spatially co-located dirty subunits of data in a sector or other unit of data for write back to a far memory of the two level memory system. In one embodiment, dirty spatially co-located subunits are scrubbed and aggregated with one or more spatially co-located dirty subunits being evicted. In one embodiment, a write combining buffer is utilized to aggregate spatially co-located dirty subunits prior to being transferred to a far memory write buffer in a write back operation. Other aspects are described herein.

公开(公告)号：US20170371795A1

公开(公告)日：2017-12-28

申请号：US15193952

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Zhe WANG ,  Christopher B. WILKERSON ,  Zeshan A. CHISHTI

IPC: G06F12/0873 ,  G06F12/123 ,  G06F12/0804

CPC classification number: G06F12/0873 ,  G06F12/0804 ,  G06F12/123 ,  G06F12/124 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/608

Abstract: An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.

公开(公告)号：US20250112772A1

公开(公告)日：2025-04-03

申请号：US18375421

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Christopher B. WILKERSON ,  Raghavan KUMAR ,  Anupam GOLDER

IPC: H04L9/30 ,  H04L9/00 ,  H04L9/08

Abstract: Bandwidth of High Bandwidth Memory (HBM) and scratch pad memory used by an Fully Homomorphic Encryption (FHE) accelerator in a System-on-Chip (SoC) during FHE relinearization is reduced by including a key generator module in the SoC. The key generator module to generate FHE public keys from a seed that is input to the SoC. The seed used by the on-die key generator module to generate FHE relinearization public keys locally within the scratch pad memory units in the SoC.

公开(公告)号：US20250112757A1

公开(公告)日：2025-04-03

申请号：US18374179

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Sanu K. MATHEW ,  Adish VARTAK ,  Christopher B. WILKERSON

IPC: H04L9/00 ,  H04L9/06

Abstract: Examples include techniques for mixed word size multiplication to facilitate operations for relinearization associated with executing a fully homomorphic encryption (FHE) workload. Examples include use of precomputed base conversion factors and decomposing large words or digits to a data size that is equal to or smaller than a machine word size associated with a multiplier datapath to facilitate the operations for relinearization.

公开(公告)号：US20250007688A1

公开(公告)日：2025-01-02

申请号：US18217561

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Sanu K. MATHEW ,  Sachin TANEJA ,  Christopher B. WILKERSON ,  Minxuan ZHOU

IPC: H04L9/00 ,  G06F17/14 ,  H04L9/30

Abstract: A reconfigurable compute circuitry to perform Fully Homomorphic Encryption (FHE) enables a full utilization of compute resources and data movement resources by mapping multiple N*1024 polynomials on to a (M*N)*1024 polynomial. To counteract the shuffling of the coefficients during Number-Theoretic-Transforms (NTT) and inverse-NTT operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.