公开(公告)号：US12182047B2

公开(公告)日：2024-12-31

申请号：US17996594

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Wee Liew ,  Ramani Tatikola ,  Edwin Thaller ,  Patrick Torta ,  Yu-Shan Wang ,  Georg Weber ,  James Yoder

IPC: G06F13/36

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

公开(公告)号：US20230236999A1

公开(公告)日：2023-07-27

申请号：US17996594

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Wee Liew ,  Ramani Tatikola ,  Edwin Thaller ,  Patrick Torta ,  Yu-Shan Wang ,  Georg Weber ,  James Yoder

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F2213/40

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.