公开(公告)号：US11489538B2

公开(公告)日：2022-11-01

申请号：US17054855

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Edwin Thaller ,  Christian Lindholm

IPC: H03M1/00 ,  H03M1/12

Abstract: A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

公开(公告)号：US20210218410A1

公开(公告)日：2021-07-15

申请号：US17054855

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Edwin Thaller ,  Christian Lindholm

IPC: H03M1/12

Abstract: A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

公开(公告)号：US12182047B2

公开(公告)日：2024-12-31

申请号：US17996594

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Wee Liew ,  Ramani Tatikola ,  Edwin Thaller ,  Patrick Torta ,  Yu-Shan Wang ,  Georg Weber ,  James Yoder

IPC: G06F13/36

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

公开(公告)号：US20230236999A1

公开(公告)日：2023-07-27

申请号：US17996594

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Wee Liew ,  Ramani Tatikola ,  Edwin Thaller ,  Patrick Torta ,  Yu-Shan Wang ,  Georg Weber ,  James Yoder

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F2213/40

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

公开(公告)号：US10651869B1

公开(公告)日：2020-05-12

申请号：US16364891

申请日：2019-03-26

Applicant: Intel IP Corporation ,  Intel Corporation

Inventor： Davide Ponton ,  Michael Kalcher ,  Alan Paussa ,  Edwin Thaller ,  Franz Kuttner ,  Daniel Gruber

IPC: H03M1/48 ,  H03M1/66 ,  H04B1/403 ,  H04B1/401 ,  H04B1/04

Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.