公开(公告)号：US12182047B2

公开(公告)日：2024-12-31

申请号：US17996594

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Wee Liew ,  Ramani Tatikola ,  Edwin Thaller ,  Patrick Torta ,  Yu-Shan Wang ,  Georg Weber ,  James Yoder

IPC: G06F13/36

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

公开(公告)号：US20230236999A1

公开(公告)日：2023-07-27

申请号：US17996594

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Wee Liew ,  Ramani Tatikola ,  Edwin Thaller ,  Patrick Torta ,  Yu-Shan Wang ,  Georg Weber ,  James Yoder

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F2213/40

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

公开(公告)号：US11901908B2

公开(公告)日：2024-02-13

申请号：US17754148

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Daniel Gruber ,  Kameran Azadet ,  Yu-Shan Wang ,  Hundo Shin ,  Martin Clara

IPC: H04B1/04 ,  H03M1/06 ,  H04B1/10

CPC classification number: H03M1/0614 ,  H04B1/0475 ,  H04B1/1018

Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

公开(公告)号：US11378999B2

公开(公告)日：2022-07-05

申请号：US16724486

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Yu-Shan Wang ,  Martin Clara ,  Daniel Gruber ,  Hundo Shin ,  Kameran Azadet

IPC: G06F1/12 ,  G06F1/14 ,  G06F1/08

Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.