公开(公告)号：US20200303822A1

公开(公告)日：2020-09-24

申请号：US16635148

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Jimin YAO ,  Shawna M. LIFF ,  William J. LAMBERT ,  Zhichao ZHANG ,  Robert L. SANKMAN ,  Sri Chaitra J. CHAVALI

IPC: H01Q9/04 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66 ,  H01L23/498

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US20200051899A1

公开(公告)日：2020-02-13

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Sanka GANESAN ,  Pilin LIU ,  Shawna LIFF ,  Sri Chaitra CHAVALI ,  Sandeep GAAN ,  Jimin YAO ,  Aastha UPPAL

IPC: H01L23/498 ,  H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20200312803A1

公开(公告)日：2020-10-01

申请号：US16363996

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jimin YAO ,  Shawna LIFF ,  Xin YAN ,  Numair AHMED

IPC: H01L23/00

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.