公开(公告)号：US20210259134A1

公开(公告)日：2021-08-19

申请号：US16794747

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Aastha UPPAL ,  Divya MANI ,  Je-Young CHANG

IPC: H05K7/20

Abstract: Embodiments disclosed herein include an integrated heat spreader (IHS). In an embodiment, the IHS comprises a main body, where the main body comprises a first surface and a second surface opposite from the second surface. In an embodiment, the IHS further and a support extending from the first surface of the main body. In an embodiment, the support comprises a shell, and a layer over an interior surface of the shell.

公开(公告)号：US20210391244A1

公开(公告)日：2021-12-16

申请号：US16898196

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Chandra Mohan JHA ,  Pooya TADAYON ,  Aastha UPPAL ,  Weihua TANG ,  Paul DIGLIO ,  Xavier BRUN

IPC: H01L23/498 ,  H01L23/373 ,  H01L23/522 ,  H01L21/56 ,  H01L21/78

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US20200051899A1

公开(公告)日：2020-02-13

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Sanka GANESAN ,  Pilin LIU ,  Shawna LIFF ,  Sri Chaitra CHAVALI ,  Sandeep GAAN ,  Jimin YAO ,  Aastha UPPAL

IPC: H01L23/498 ,  H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20210111091A1

公开(公告)日：2021-04-15

申请号：US16600107

申请日：2019-10-11

Applicant: Intel Corporation

Inventor： Aastha UPPAL ,  Divya MANI ,  Je-Young CHANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/433 ,  H01L23/373 ,  H01L23/10 ,  H01L21/48 ,  H01L25/00

Abstract: Embodiments include semiconductor packages. A semiconductor package include a high-power electronic component and an embedded heat spreader (EHS) in a package substrate. The EHS is adjacent to the high-power electronic component. The semiconductor package includes a plurality of thermal interconnects below the EHS and the package substrate, and a plurality of dies on the package substrate. The thermal interconnects is coupled to the EHS. The EHS is below the high-power electronic component and embedded within the package substrate. The high-power electronic component has a bottom surface substantially proximate to a top surface of the EHS. The EHS is a copper heat sink, and the high-power electronic component is an air core inductor or a voltage regulator. The thermal interconnects are comprised of thermal ball grid array balls or thermal adhesive materials. The thermal interconnects couple a bottom surface of the package substrate to a top surface of a substrate.

公开(公告)号：US20200043894A1

公开(公告)日：2020-02-06

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George VAKANAS ,  Aastha UPPAL ,  Shereen ELHALAWATY ,  Aaron MCCANN ,  Edvin CETEGEN ,  Tannaz HARIRCHIAN ,  Saikumar JAYARAMAN

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.