公开(公告)号：US20200051899A1

公开(公告)日：2020-02-13

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Sanka GANESAN ,  Pilin LIU ,  Shawna LIFF ,  Sri Chaitra CHAVALI ,  Sandeep GAAN ,  Jimin YAO ,  Aastha UPPAL

IPC: H01L23/498 ,  H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20190393606A1

公开(公告)日：2019-12-26

申请号：US16017093

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Sri Chaitra CHAVALI ,  Siddharth ALUR ,  Sheng LI

IPC: H01Q9/04 ,  H01Q5/35 ,  H01L23/66

Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.

公开(公告)号：US20190311916A1

公开(公告)日：2019-10-10

申请号：US16317789

申请日：2016-07-14

Applicant: Intel Corporation

Inventor： Sri Chaitra CHAVALI ,  Siddharth K. ALUR ,  Amanda E. SCHUCKMAN ,  Amruthavalli Palla ALUR ,  Islam A. SALAMA ,  Yikang DENG ,  Kristof DARMAWIKARTA

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimageable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.