公开(公告)号：US20220416998A1

公开(公告)日：2022-12-29

申请号：US17356168

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Dumitru-Daniel Dinu ,  Joseph Friel ,  Avinash L. Varna ,  Manoj Sastry

IPC: H04L9/06 ,  G06F21/72 ,  H04L9/00

Abstract: In one example an apparatus comprises an input state register, and a first round secure hash algorithm (SHA) datapath circuit communicatively coupled to the input state register and a second round secure hash algorithm (SHA) datapath circuit communicatively coupled to the first round secure hash datapath circuit, the first round secure has algorithm (SHA) datapath circuit and the second round secure hash algorithm (SHA) datapath circuit each comprising a first section to perform a θ step of a SHA calculation, a second section to perform a ρ step calculation, a third section to perform a π step of the SHA calculation, a fourth section to perform a χ step of the SHA calculation, and a fifth section to perform a ι step of the SHA calculation.

公开(公告)号：US11424907B2

公开(公告)日：2022-08-23

申请号：US16911261

申请日：2020-06-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Joseph Friel ,  Avinash Laxmisha Varna ,  Manoj Sastry

IPC: H04L9/00 ,  G06F7/72 ,  H04L9/08 ,  H04L9/32

Abstract: Embodiments are directed to countermeasures for side-channel attacks on protected sign and key exchange operations. An embodiment of storage mediums includes instructions for commencing a process including an elliptic curve scalar multiplication (ESM) operation including application of a secret scalar value; splitting the secret scalar value into two random scalar values; counting a number of leading ‘0’ bits in the scalar value and skipping the number of leading ‘0’ bits in processing; performing an ESM iteration for each bit of the secret scalar value beginning with a most significant ‘1’ bit of the scalar value including a Point Addition operation and a Point Double operation for each bit on randomized points; performing ESM operation dummy iterations equal to the number of leading ‘0’ bits; and returning an output result for the ESM operation.

公开(公告)号：US11216594B2

公开(公告)日：2022-01-04

申请号：US16456308

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Debayan Das ,  Carlos Tokunaga ,  Avinash L. Varna ,  Joseph Friel

IPC: G06F21/72 ,  G06F21/12 ,  G06F21/64

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.

公开(公告)号：US20210409188A1

公开(公告)日：2021-12-30

申请号：US16911261

申请日：2020-06-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Joseph Friel ,  Avinash Laxmisha Varna ,  Manoj Sastry

IPC: H04L9/00 ,  G06F7/72 ,  H04L9/08 ,  H04L9/32

Abstract: Embodiments are directed to countermeasures for side-channel attacks on protected sign and key exchange operations. An embodiment of storage mediums includes instructions for commencing a process including an elliptic curve scalar multiplication (ESM) operation including application of a secret scalar value; splitting the secret scalar value into two random scalar values; counting a number of leading ‘0’ bits in the scalar value and skipping the number of leading ‘0’ bits in processing; performing an ESM iteration for each bit of the secret scalar value beginning with a most significant ‘1’ bit of the scalar value including a Point Addition operation and a Point Double operation for each bit on randomized points; performing ESM operation dummy iterations equal to the number of leading ‘0’ bits; and returning an output result for the ESM operation.

公开(公告)号：US20190318130A1

公开(公告)日：2019-10-17

申请号：US16456308

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Debayan Das ,  Carlos Tokunaga ,  Avinash L. Varna ,  Joseph Friel

IPC: G06F21/72 ,  G06F21/64 ,  G06F21/12

Abstract: Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.