公开(公告)号：US20170147356A1

公开(公告)日：2017-05-25

申请号：US15300086

申请日：2014-04-28

Applicant: INTEL CORPORATION

Inventor： Karunakara KOTARY ,  Nicholas J. YOKE ,  Brett P. WANG ,  Genliu XING

IPC: G06F9/44 ,  G06F12/14 ,  G06F3/06 ,  G06F21/57 ,  H04L9/32

CPC classification number: G06F9/4401 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/068 ,  G06F12/1408 ,  G06F21/575 ,  G06F21/72 ,  G06F2212/1052 ,  H04L9/3242

Abstract: Technologies for securely booting a computing device includes a security engine of the computing device that consecutively determines a hash value for each block of initial boot firmware and generates an aggregated hash value from the hash value determined for each of the blocks. A processor of the computing device determines whether the aggregated hash value matches a reference checksum value. Initialization of the processor is completed in response to a determination that the aggregated hash value matches the reference checksum value. In some embodiments, the security engine consecutively retrieves each block of the initial boot firmware from a memory of the computing device, stores each retrieved block in a secure memory of the security engine, and determines the hash value for each stored block. Each block stored in the secure memory is copied to a portion of a cache memory of the processor initialized as Cache as RAM.

公开(公告)号：US20220326962A1

公开(公告)日：2022-10-13

申请号：US17847166

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Navneeth JAYARAJ ,  Richard Marian THOMAIYAR ,  Ashraf JAVEED ,  Vikas MISHRA ,  Rajesh POORNACHANDRAN ,  Mahammad Yaseen Isasaheb MULLA ,  Laxminarayan KAMATH ,  Karunakara KOTARY ,  Dustin FREDRICKSON

IPC: G06F9/4401 ,  G06F1/28

Abstract: An apparatus is described. The apparatus includes an accelerator having an interface to plug into an electronic system. The accelerator includes a field programmable gate array integrated circuit to perform acceleration, a general purpose processor integrated circuit to execute software related to the acceleration and controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.

公开(公告)号：US20240143376A1

公开(公告)日：2024-05-02

申请号：US18337089

申请日：2023-06-19

Applicant: Intel Corporation

Inventor： Rajesh POORNACHANDRAN ,  Karunakara KOTARY ,  Arun Kumar SINGH

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45595

Abstract: It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to receive a request of a virtual machine to access a resource of a network node, determine whether a number of available virtual functions associated to the resource falls below a predefined threshold and, if it is determined that the number of available virtual functions falls below the predefined threshold, emulate and/or para virtualize a physical function associated to the resource. The machine-readable instructions further comprise instructions to provide access to the resource via the emulated and/or para virtualized physical function for the virtual machine.