公开(公告)号：US20200210113A1

公开(公告)日：2020-07-02

申请号：US16818637

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Yu Bai ,  Kermin Chofleming

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of memory operations associated with a data-flow graph that represents a computer code, where a spatial architecture executes the data-flow graph and the spatial architecture includes a plurality of memory controllers, randomly assigns one or more of the plurality of memory operations to one or more of the plurality of memory controllers to generate a first allocation of the plurality of memory operations to the memory controllers, and determines that the first allocation is to be stored as a permanent memory allocation based on a first performance metric associated with the first allocation.

公开(公告)号：US11249683B2

公开(公告)日：2022-02-15

申请号：US16818637

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Yu Bai ,  Kermin Chofleming

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of memory operations associated with a data-flow graph that represents a computer code, where a spatial architecture executes the data-flow graph and the spatial architecture includes a plurality of memory controllers, randomly assigns one or more of the plurality of memory operations to one or more of the plurality of memory controllers to generate a first allocation of the plurality of memory operations to the memory controllers, and determines that the first allocation is to be stored as a permanent memory allocation based on a first performance metric associated with the first allocation.

公开(公告)号：US12204478B2

公开(公告)日：2025-01-21

申请号：US17206961

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Swapna Raj ,  Samantika S. Sury ,  Kermin Chofleming ,  Simon C. Steely, Jr.

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16

Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.