公开(公告)号：US20230367640A1

公开(公告)日：2023-11-16

申请号：US18030057

申请日：2021-04-23

Applicant: Intel Corporation

Inventor： Kermin E. ChoFleming, Jr. ,  Egor A. Kazachkov ,  Daya Shanker Khudia ,  Zakhar A. Matveev ,  Sergey U. Kokljuev ,  Fabrizio Petrini ,  Dmitry S. Petrov ,  Swapna Raj

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/5044 ,  G06F11/302 ,  G06F11/3409 ,  G06F2209/509 ,  G06F2201/865

Abstract: An offload analyzer analyzes a program for porting to a heterogenous computing system by identifying code objects for offloading to an accelerator. Runtime metrics generated by executing the program on a host processor unit are provided to an accelerator model that models the performance of the accelerator and generates estimated accelerator metrics for the program. A code object offload selector selects code objects for offloading based on whether estimated accelerated times of the code objects, which comprise estimated accelerator times and offload overhead times, are better than their host processor unit execution times. The code object offload selector selects additional code objects for offloading using a dynamic-programming-like performance estimation approach that performs a bottom-up traversal of a call tree. A heterogeneous version of the program can be generated for execution on the heterogeneous computing system.

公开(公告)号：US20220222177A1

公开(公告)日：2022-07-14

申请号：US17710524

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Kermin ChoFleming ,  Swapna Raj

IPC: G06F12/0806

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for improving data transfer for heterogeneous programs. An example apparatus includes instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to determine a runtime associated with executing a code object by a heterogeneous electronic device based on at least one of a location of a memory object or a data transfer penalty, the data transfer penalty associated with access of the memory object in response to execution of the code object, identify a memory operation for the memory object based on the runtime, and generate an executable file based on the memory operation, the executable file, when executed, to cause execution of the code object by at least one of first hardware or second hardware of the heterogeneous electronic device based on the memory operation.

公开(公告)号：US12204478B2

公开(公告)日：2025-01-21

申请号：US17206961

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Swapna Raj ,  Samantika S. Sury ,  Kermin Chofleming ,  Simon C. Steely, Jr.

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16

Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.