公开(公告)号：US20240411978A1

公开(公告)日：2024-12-12

申请号：US18331958

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Markus SCHWIEGERSHAUSEN ,  Krzysztof DOMANSKI

IPC: G06F30/398 ,  G06F30/31 ,  G06F30/392

Abstract: A method to manufacture an integrated semiconductor device is provided, the method including: select a plurality of integrated circuit semiconductor device component layouts of an entity of integrated circuit semiconductor device component layouts based on a shared set of parameters; perform at least one compatibility verification process for the selected plurality of integrated circuit semiconductor device component layouts with regard to an environment of the integrated circuit semiconductor device component at a predetermined position in an integrated circuit semiconductor device; and output a compatibility verification information indicating a result of the at least one compatibility verification process for the plurality of integrated circuit semiconductor device component layouts.

公开(公告)号：US20250005254A1

公开(公告)日：2025-01-02

申请号：US18342756

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Nicolas RICHAUD ,  Krzysztof DOMANSKI ,  Michael LANGENBUCH

IPC: G06F30/398 ,  G06F30/392

Abstract: A non-transitory computer readable medium is provided having instructions stored therein that when executed by a processor cause the processor to select a device interface component layout from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to an interface structure of a shared integrated circuit semiconductor device component; perform at least one compatibility verification process for the selected device interface component layout with regard to an environment of the device interface component at a predetermined position in the integrated circuit semiconductor device; and output a compatibility verification information indicating a result of the at least one compatibility verification process for the selected device interface component layout.

公开(公告)号：US20250004035A1

公开(公告)日：2025-01-02

申请号：US18343763

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Krzysztof DOMANSKI ,  Manhar MUDDU

IPC: G01R31/26

Abstract: A non-transitory computer readable medium is provided. The non-transitory computer readable medium having instructions stored therein that when executed by a processor cause the processor to: receive current information of a semiconductor device, calculate an absolute current value of the semiconductor device from the current information and compare the absolute current value with a first threshold; receive information regarding a duration of a forward bias of the semiconductor device and compare the duration with a second threshold if the absolute current value is more than the first threshold; perform a layout review of tap spacing of selected semiconductor device components; and output safe operation area (SOA) information indicating a forward bias junction result based on the absolute current value, the duration of forward bias and the layout review.