公开(公告)号：US20250113547A1

公开(公告)日：2025-04-03

申请号：US18375064

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Tao CHU ,  Chiao-Ti HUANG ,  Guowei XU ,  Robin CHAO ,  Feng ZHANG ,  Yue ZHONG ,  Yang ZHANG ,  Ting-Hsiang HUNG ,  Kevin P. O’BRIEN ,  Uygar E. AVCI ,  Carl H. NAYLOR ,  Mahmut Sami KAVRIK ,  Andrey VYATSKIKH ,  Rachel STEINHARDT ,  Chelsey DOROW ,  Kirby MAXEY

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.