公开(公告)号：US20170317172A1

公开(公告)日：2017-11-02

申请号：US15650569

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Jack T. KAVALIEROS ,  Nancy ZELICK ,  Been-Yih JIN ,  Markus KUHN ,  Stephen M. CEA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.