公开(公告)号：US09013941B2

公开(公告)日：2015-04-21

申请号：US13839174

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Swaroop Ghosh ,  Mesut Meterelliyoz ,  Faith Hamzaoglu ,  Yih Wang ,  Kevin X. Zhang

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/56 ,  G11C7/06 ,  G11C7/08

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C11/5642

Abstract: Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and second DRAM bitlines; and a circuit having a trigger node coupled to the sense amp to transition it from a first state to a second state to trigger the sense amp, the circuit having an element to impede the transition once it is initiated. A chip is described which comprises: a DRAM array having a plurality of bitlines; sense amplifiers to resolve data on the bit lines, and a circuit to slow down resolution of the data by the sense amps after they have been triggered to resolve the data.

Abstract translation: 公开了用于解析位线上的数据的脉冲读出放大器方法。 提供了一种芯片，其包括耦合到第一和第二DRAM位线的读出放大器; 以及电路，其具有耦合到所述感测放大器的触发节点，以将其从第一状态转换到第二状态以触发所述感测放大器，所述电路具有阻止所述转换的元件。 描述了一种芯片，其包括：具有多个位线的DRAM阵列; 用于解析位线上的数据的读出放大器，以及在触发解调数据之后通过感测放大器降低数据分辨率的电路。