公开(公告)号：US20150348623A1

公开(公告)日：2015-12-03

申请号：US14290623

申请日：2014-05-29

Applicant: Intel Corporation

Inventor： Blake Lin ,  Cyrille Dray ,  Ananda Roy ,  Liqiong Wei ,  Faith Hamzaoglu

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0066 ,  G11C2013/0078

Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.

Abstract translation: 描述了用于提高电阻式存储器能量效率和可靠性的装置和方法。 一种装置可以包括耦合到导线的电阻式存储单元。 该装置还可以包括耦合到导线的驱动器，以在写操作期间驱动电阻性存储单元的电流。 在用于检测导线上的电压变化的写入操作期间，可以选择性地增加驱动器的电阻两个或更多个时间段。 当检测到电压变化以提高电阻性存储器的能量效率和可靠性时，用于写入操作的电流可以被关闭。

公开(公告)号：US09013941B2

公开(公告)日：2015-04-21

申请号：US13839174

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Swaroop Ghosh ,  Mesut Meterelliyoz ,  Faith Hamzaoglu ,  Yih Wang ,  Kevin X. Zhang

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/56 ,  G11C7/06 ,  G11C7/08

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C11/5642

Abstract: Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and second DRAM bitlines; and a circuit having a trigger node coupled to the sense amp to transition it from a first state to a second state to trigger the sense amp, the circuit having an element to impede the transition once it is initiated. A chip is described which comprises: a DRAM array having a plurality of bitlines; sense amplifiers to resolve data on the bit lines, and a circuit to slow down resolution of the data by the sense amps after they have been triggered to resolve the data.

Abstract translation: 公开了用于解析位线上的数据的脉冲读出放大器方法。 提供了一种芯片，其包括耦合到第一和第二DRAM位线的读出放大器; 以及电路，其具有耦合到所述感测放大器的触发节点，以将其从第一状态转换到第二状态以触发所述感测放大器，所述电路具有阻止所述转换的元件。 描述了一种芯片，其包括：具有多个位线的DRAM阵列; 用于解析位线上的数据的读出放大器，以及在触发解调数据之后通过感测放大器降低数据分辨率的电路。