公开(公告)号：US20170212832A1

公开(公告)日：2017-07-27

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/42 ,  G06F13/12 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US09910771B2

公开(公告)日：2018-03-06

申请号：US15396732

申请日：2017-01-02

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

公开(公告)号：US09535829B2

公开(公告)日：2017-01-03

申请号：US14128669

申请日：2013-07-26

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Robert J. Royer, Jr. ,  Michael W. Williams ,  Jeffrey R. Wilcox ,  Ritesh B. Trivedi ,  Blaise Fanning

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/02 ,  G06F13/12 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/38 ,  G06F13/4234 ,  G06F2212/7202

Abstract: In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

Abstract translation: 在一个实施例中，存储器接口可以发送请求被发送的指示。 该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。 存储器接口可以经由总线将请求发送到非易失性存储器。 请求可以包括可用于标识用于存储或读取数据的位置的地址。 非易失性存储器可以从总线获取请求并处理请求。 在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。 存储器接口可以向总线授予对非易失性存储器的访问。 在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

公开(公告)号：US09036718B2

公开(公告)日：2015-05-19

申请号：US14132703

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： David J. Zimmerman ,  Michael W. Williams

IPC: H04B3/00 ,  H04L25/00 ,  G06F13/28 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F13/28 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.