公开(公告)号：US20250037347A1

公开(公告)日：2025-01-30

申请号：US18358297

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Supratim Pal ,  Kevin Hurd ,  Jorge E. Parra Osorio ,  Christopher Spencer ,  Takashi Nakagawa ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Clifford Gibson ,  Li-An Tang ,  Fangwen Fu ,  Kaiyu Chen ,  Buqi Cheng

IPC: G06T15/00 ,  G06F9/30

Abstract: Described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. The integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single instruction.

公开(公告)号：US20250036412A1

公开(公告)日：2025-01-30

申请号：US18358308

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Jiasheng Chen ,  Christopher Spencer ,  Jorge E. Parra Osorio ,  Kevin Hurd ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  Fangwen Fu ,  Wei Xiong ,  Hongzheng Li ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Shuai Mu ,  Clifford Gibson ,  Buqi Cheng

IPC: G06F9/30 ,  G06F9/38

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a plurality of processing resources. A processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data elements specified by the source operand from a first format of a plurality of datatype formats to a second format of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

公开(公告)号：US20250036361A1

公开(公告)日：2025-01-30

申请号：US18358304

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Jiasheng Chen ,  Kevin Hurd ,  Jorge E. Parra Osorio ,  Christopher Spencer ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  Fangwen Fu ,  Wei Xiong ,  Hongzheng Li ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Shuai Mu ,  Clifford Gibson ,  Buqi Cheng

IPC: G06F7/483

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.