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    Hierarchical thread scheduling based on multiple barriers
    2.
    发明授权
    Hierarchical thread scheduling based on multiple barriers 有权

    公开(公告)号：US11977895B2

    公开(公告)日：2024-05-07

    申请号：US17131647

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Sabareesh Ganapathy ,  Fangwen Fu ,  Hong Jiang ,  James Valerio

    IPC: G06F9/38 ,  G06F9/48 ,  G06F9/54 ,  G06T1/20

    CPC classification number: G06F9/3838 ,  G06F9/4881 ,  G06F9/544 ,  G06T1/20

    Abstract: Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

    SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCESSING
    3.
    发明公开
    SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCESSING 审中-公开

    公开(公告)号：US20240111609A1

    公开(公告)日：2024-04-04

    申请号：US17958213

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Biju George ,  Supratim Pal ,  James Valerio ,  Vasanth Ranganathan ,  Fangwen Fu ,  Chunhui Mei

    IPC: G06F9/52 ,  G06F9/30

    CPC classification number: G06F9/522 ,  G06F9/30098

    Abstract: Low-latency synchronization utilizing local team barriers for thread team processing is described. An example of an apparatus includes one or more processors including a graphics processor, the graphics processor including a plurality of processing resources; and memory for storage of data including data for graphics processing, wherein the graphics processor is to receive a request for establishment of a local team barrier for a thread team, the thread team being allocated to a first processing resource, the thread team including multiple threads; determine requirements and designated threads for the local team barrier; and establish the local team barrier in a local register of the first processing resource based at least in part on the requirements and designated threads for the local barrier.

    PARTIAL WRITE MANAGEMENT IN A MULTI-TILED COMPUTE ENGINE
    8.
    发明申请
    PARTIAL WRITE MANAGEMENT IN A MULTI-TILED COMPUTE ENGINE 有权

    公开(公告)号：US20210056028A1

    公开(公告)日：2021-02-25

    申请号：US17068754

    申请日：2020-10-12

    Applicant: Intel Corporation

    Inventor： JOYDEEP RAY ,  James Valerio ,  Ben Ashbaugh ,  Lakshminarayanan Striramassarma

    IPC: G06F12/0811 ,  G06F3/06 ,  G06F9/38 ,  G06F9/54

    Abstract: Embodiments described herein provide a general purpose graphics processor comprising a plurality of tiles, each tile of the plurality of tiles comprising at least one execution unit, a local cache, and a cache control unit, and a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles. The cache control unit is to implement a partial write management protocol to receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data, write the data associated with the partial write operation to the local cache when the cache line is in a modified state, and forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state. Other embodiments may be described and claimed.

    Microcontroller-based flexible thread scheduling launching in computing environments
    9.
    发明授权
    Microcontroller-based flexible thread scheduling launching in computing environments 有权

    公开(公告)号：US10402224B2

    公开(公告)日：2019-09-03

    申请号：US15860708

    申请日：2018-01-03

    Applicant: Intel Corporation

    Inventor： Kiran C. Veernapu ,  Kamlesh Pillai ,  James Valerio ,  Joydeep Ray ,  Abhishek Appu

    IPC: G06F9/48 ,  G06F9/54 ,  G06T1/20 ,  G06F9/22 ,  G06T15/00

    Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.

    Instruction prefetch based on thread dispatch commands
    10.
    发明授权
    Instruction prefetch based on thread dispatch commands 有权

    公开(公告)号：US12124852B2

    公开(公告)日：2024-10-22

    申请号：US18347964

    申请日：2023-07-06

    Applicant: Intel Corporation

    Inventor： James Valerio ,  Vasanth Ranganathan ,  Joydeep Ray ,  Pradeep Ramani

    IPC: G06F9/44 ,  G06F9/38 ,  G06F13/28 ,  G06T1/20

    CPC classification number: G06F9/3802 ,  G06F13/28 ,  G06T1/20

    Abstract: A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. The circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and prefetch the data identified by the event into a second cache that is local to the second compute unit before an attempt to read the instruction or data by the second thread.

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