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公开(公告)号:US20210407997A1
公开(公告)日:2021-12-30
申请号:US16912113
申请日:2020-06-25
Applicant: Intel Corporation
Inventor: Nicole THOMAS , Ehren MANNEBACH , Cheng-Ying HUANG , Marko RADOSAVLJEVIC
IPC: H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786 , H01L21/02 , H01L21/8238 , H01L29/66
Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
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公开(公告)号:US20240332389A1
公开(公告)日:2024-10-03
申请号:US18736428
申请日:2024-06-06
Applicant: Intel Corporation
Inventor: Nicole THOMAS , Michael K. HARPER , Leonard P. GULER , Marko RADOSAVLJEVIC , Thoe MICHAELOS
IPC: H01L29/423 , H01L21/02 , H01L21/768 , H01L21/8234 , H01L29/06
CPC classification number: H01L29/42392 , H01L21/0228 , H01L21/76897 , H01L21/823412 , H01L29/0669
Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
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公开(公告)号:US20220262796A1
公开(公告)日:2022-08-18
申请号:US17731110
申请日:2022-04-27
Applicant: Intel Corporation
Inventor: Nicole THOMAS , Ehren MANNEBACH , Cheng-Ying HUANG , Marko RADOSAVLJEVIC
IPC: H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02 , H01L21/8238
Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
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公开(公告)号:US20240088153A1
公开(公告)日:2024-03-14
申请号:US18513028
申请日:2023-11-17
Applicant: Intel Corporation
Inventor: Nicole THOMAS , Ehren MANNEBACH , Cheng-Ying HUANG , Marko RADOSAVLJEVIC
IPC: H01L27/092 , H01L21/02 , H01L21/8238 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786
CPC classification number: H01L27/0922 , H01L21/02236 , H01L21/02532 , H01L21/02603 , H01L21/823807 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66742 , H01L29/78618 , H01L29/78696
Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
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公开(公告)号:US20210408257A1
公开(公告)日:2021-12-30
申请号:US16911705
申请日:2020-06-25
Applicant: Intel Corporation
Inventor: Nicole THOMAS , Michael K. HARPER , Leonard P. GULER , Marko RADOSAVLJEVIC , Thoe MICHAELOS
IPC: H01L29/423 , H01L29/06 , H01L21/8234 , H01L21/768 , H01L21/02
Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.
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