公开(公告)号：US20240355625A1

公开(公告)日：2024-10-24

申请号：US18758948

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28185 ,  H01L21/02603 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

Abstract: A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.

公开(公告)号：US20240332423A1

公开(公告)日：2024-10-03

申请号：US18739078

申请日：2024-06-10

Applicant: Epinovatech AB

Inventor： Martin Andreas Olsson

IPC: H01L29/78 ,  G01N27/414 ,  G06N10/00 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/417 ,  H01L29/775 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32 ,  H10N60/10 ,  H10N60/83 ,  H10N60/85

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/0924 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/20 ,  H01L29/775 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32 ,  H10N60/128 ,  H10N60/83 ,  H10N60/85 ,  G01N27/4146 ,  G06N10/00 ,  H01L29/41791

Abstract: A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer. The FinFET transistor comprising: a fin semiconductor structure comprising an elongate protruding core portion, the fin semiconductor structure being arranged on the lattice-mismatched semiconductor epilayer, a first and a second nanostructured electrode radially enclosing respectively a source end and a drain end of the protruding core portion, and a nanostructured gate electrode radially enclosing a central portion of the protruding core portion, the central portion being a portion of the protruding core portion between the source end and the drain end.

公开(公告)号：US20240332187A1

公开(公告)日：2024-10-03

申请号：US18740024

申请日：2024-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/30625 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.

公开(公告)号：US12078551B2

公开(公告)日：2024-09-03

申请号：US17069596

申请日：2020-10-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zi-Ang Su ,  Ming-Shuan Li ,  Shu-Hua Wu ,  Chih Chieh Yeh ,  Chih-Hung Wang ,  Wen-Hsing Hsieh

IPC: G01K7/01 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

CPC classification number: G01K7/015 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26513 ,  H01L21/82285 ,  H01L27/0826 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.

公开(公告)号：US12069865B2

公开(公告)日：2024-08-20

申请号：US17567586

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L51/30 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B51/30 ,  H10B99/00

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78696 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

公开(公告)号：US12068321B2

公开(公告)日：2024-08-20

申请号：US18347023

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Soonmoon Jung

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/18 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/187 ,  H01L21/28088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes a first transistor, a division pattern, and a second transistor sequentially stacked on a substrate. The first transistor includes a first gate structure, a first source/drain layer at each of opposite sides of the first gate structure, and first semiconductor patterns spaced apart from each other in a vertical direction. Each of the first semiconductor patterns extends through the first gate structure and contacts the first source/drain layer. The division pattern includes an insulating material. The second transistor includes a second gate structure, a second source/drain layer at each of opposite sides of the second gate structure, and second semiconductor patterns spaced apart from each other in the vertical direction. Each of the second semiconductor patterns extends through the second gate structure and contacts the second source/drain layer. The first source/drain layer does not directly contact the second source/drain layer.

公开(公告)号：US20240276697A1

公开(公告)日：2024-08-15

申请号：US18641904

申请日：2024-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696 ,  H10B10/18

Abstract: An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.

公开(公告)号：US20240274604A1

公开(公告)日：2024-08-15

申请号：US18625282

申请日：2024-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mao-Lin HUANG ,  Jia-Ni YU ,  LUNG-KUN CHU ,  Chung-Wei HSU ,  Chih-Hao WANG ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device structure is provided. The structure includes a first gate electrode layer having at least three surfaces surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material. The structure also includes a second gate electrode layer disposed below and in contact with the first gate electrode layer, the second gate electrode layer having at least three surfaces surrounded by a second intermixed layer, wherein the second intermixed layer comprises the first material and a fifth material, wherein the first gate electrode layer and the second gate electrode layer are disposed between two adjacent dielectric spacers.

公开(公告)号：US20240258323A1

公开(公告)日：2024-08-01

申请号：US18631351

申请日：2024-04-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE

IPC: H01L27/12 ,  H01L21/02 ,  H01L27/088 ,  H01L29/04 ,  H01L29/24 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/0883 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/045 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L21/02603 ,  H01L29/04 ,  H01L29/4908 ,  H01L2924/13069

Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

公开(公告)号：US12041859B2

公开(公告)日：2024-07-16

申请号：US18192554

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Steven J. Holmes ,  Devendra K. Sadana ,  Ning Li ,  Stephen W. Bedell

IPC: H01L21/02 ,  G06N10/00 ,  H01L39/02 ,  H10N60/01 ,  H10N60/12 ,  H10N60/80 ,  H10N60/81

CPC classification number: H10N60/805 ,  G06N10/00 ,  H10N60/0884 ,  H10N60/0912 ,  H10N60/12 ,  H10N60/815 ,  H01L21/02603 ,  H01L2221/1094

Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.