公开(公告)号：US20240203869A1

公开(公告)日：2024-06-20

申请号：US18067031

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Nikhil Jasvant Mehta ,  Charles Henry Wallace

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76892 ,  H01L23/53228 ,  H01L23/53257

Abstract: Methods for fabricating an integrated circuit (IC) device with one or more hybrid metal lines are provided. An example IC device includes a substrate; and a metal line extending, along an axis, over the substrate. The metal line has a first end and a second end along the axis. A portion of the metal line at the first end includes a first electrically conductive material. Another portion of the metal line includes a second electrically conductive material, where the second electrically conductive material is different from the first electrically conductive material. In some instances, the first electrically conductive material is a low-resistive, electrically conductive material, and the second electrically conductive material is a direct etch-compatible, electrically conductive material.

公开(公告)号：US20240105589A1

公开(公告)日：2024-03-28

申请号：US17936014

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Shao Ming Koh ,  Patrick Morrow ,  June Choi ,  Sukru Yemenicioglu ,  Nikhil Jasvant Mehta

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/528

Abstract: An IC device includes a metal layer that includes staggered metal lines. The metal lines are in two or more levels along a direction. There may be one or more metal lines in each level. At least some of the metal lines are aligned along the direction so that widths of the metal lines may be maximized for a given total width of the metal layer. The alignment of the metal lines may be achieved through DSA of a diblock copolymer. The metal layer may be connected to vias in two or more levels. The vias may be also connected to another metal layer or a semiconductor device in a FEOL section of the IC device. A via and the metal line connected to the via may be formed through a same recess and deposition process to eliminate interface between the via and metal line.

公开(公告)号：US20240096785A1

公开(公告)日：2024-03-21

申请号：US17933000

申请日：2022-09-16

Applicant: Intel Corporation

Inventor： June Choi ,  Charles Henry Wallace ,  Richard E. Schenker ,  Nikhil Jasvant Mehta

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242

Abstract: An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.