公开(公告)号：US20220091168A1

公开(公告)日：2022-03-24

申请号：US17543956

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Yossi Ben Simon ,  Ido Kahan ,  Ofir Shwartz ,  Ernest Knoll ,  Assaf Admoni

IPC: G01R23/02 ,  G06F1/12

Abstract: An apparatus comprising a frequency monitor circuitry to receive a first clock signal, a second clock signal and an expected frequency ratio, determine whether a ratio between the first clock signal and the second clock signal matches an expected an expected frequency ratio and generate an error signal upon a determination that the ratio between the first clock signal and the second clock signal does not match the expected frequency ratio.

公开(公告)号：US12177343B2

公开(公告)日：2024-12-24

申请号：US17358952

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Baiju Patel ,  Siddhartha Chhabra ,  Prashant Dewan ,  Ofir Shwartz

IPC: H04L9/08

Abstract: Systems, methods, and apparatuses for providing chiplet binding to a disaggregated architecture for a system on a chip are described. In one embodiment, system includes a plurality of physically separate dies, an interconnect to electrically couple the plurality of physically separate dies together, a first die-to-die communication circuit, of a first die of the plurality of physically separate dies, comprising a transmitter circuit and an encryption circuit having a link key to encrypt data to be sent from the transmitter circuit into encrypted data, and a second die-to-die communication circuit, of a second die of the plurality of physically separate dies, comprising a receiver circuit and a decryption circuit having the link key to decrypt the encrypted data sent from the transmitter circuit to the receiver circuit.

公开(公告)号：US20230092152A1

公开(公告)日：2023-03-23

申请号：US17482965

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Ofir Shwartz ,  David Deitcher

IPC: G06F21/62 ,  G06F21/44 ,  G06F21/60 ,  G06F12/14

Abstract: An embodiment of an integrated circuit may comprise a management controller and circuitry communicatively coupled to the management controller, the circuitry to apply two or more respective controls to statistical data from two or more respective data sources in accordance with respective configuration information for each data source, and store the statistical data in a memory in accordance with the applied two or more controls. Other embodiments are disclosed and claimed.

公开(公告)号：US20210319138A1

公开(公告)日：2021-10-14

申请号：US17358287

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Prashant Dewan ,  Baiju Patel ,  Siddhartha Chhabra ,  Ofir Shwartz ,  Kumar Dwarakanath

IPC: G06F21/72 ,  G06F21/79 ,  G06F21/73 ,  G06F21/60 ,  G06F15/78 ,  G06F7/58

Abstract: Methods and apparatus relating to utilization of logic and a serial number to provide persistent unique platform secret for generation of System on Chip (SOC or SoC) root keys are described. In an embodiment, stepping logic circuitry generates a stepping identifier in response to a first signal. Unique identifier logic circuitry generates a unique identifier in response to a second signal. Secret generation logic circuitry generates a key based at least in part on the stepping identifier and the unique identifier. The unique identifier is stored in persistent memory. Other embodiments are also disclosed and claimed.