公开(公告)号：US20240186395A1

公开(公告)日：2024-06-06

申请号：US18076130

申请日：2022-12-06

Applicant: Intel Corporation

Inventor： Krishna GANESAN ,  Ala ALAZIZI ,  Ankit Kirit LAKHANI ,  Peter P. SUN ,  Diana Ivonne PAREDES

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Lined conductive via structures for trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures over corresponding ones of a plurality of vertical stacks of horizontal nanowires. The integrated circuit structure also includes a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion over a lower portion, the upper portion of each of the plurality of conductive trench contact structures having a length between ends. The integrated circuit structure also includes a dielectric liner in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures.