公开(公告)号：US20250081597A1

公开(公告)日：2025-03-06

申请号：US18240106

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Anindya DASGUPTA ,  Ankit Kirit LAKHANI ,  Guanqun CHEN ,  Ian TOLLE ,  Saurabh ACHARYA ,  Shengsi LIU ,  Baofu ZHU ,  Nikhil MEHTA ,  Krishna GANESAN ,  Charles H. WALLACE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

公开(公告)号：US20240186395A1

公开(公告)日：2024-06-06

申请号：US18076130

申请日：2022-12-06

Applicant: Intel Corporation

Inventor： Krishna GANESAN ,  Ala ALAZIZI ,  Ankit Kirit LAKHANI ,  Peter P. SUN ,  Diana Ivonne PAREDES

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Lined conductive via structures for trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures over corresponding ones of a plurality of vertical stacks of horizontal nanowires. The integrated circuit structure also includes a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion over a lower portion, the upper portion of each of the plurality of conductive trench contact structures having a length between ends. The integrated circuit structure also includes a dielectric liner in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures.

公开(公告)号：US20240105801A1

公开(公告)日：2024-03-28

申请号：US17951974

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Raghuram GANDIKOTA ,  Krishna GANESAN ,  Sean PURSEL

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775 ,  H01L2029/42388

Abstract: Integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. A dielectric backbone structure is along the first side of the stack of nanowires. The dielectric backbone structure has a bottom above a bottom of the sub-fin. A gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires.

公开(公告)号：US20230290843A1

公开(公告)日：2023-09-14

申请号：US17693124

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Krishna GANESAN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088

CPC classification number: H01L29/41783 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/413

Abstract: Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

公开(公告)号：US20220399373A1

公开(公告)日：2022-12-15

申请号：US17348000

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Chanaka MUNASINGHE ,  Makram ABD EL QADER ,  Marie CONTE ,  Saurabh MORARKA ,  Elliot N. TAN ,  Krishna GANESAN ,  Mohit K. HARAN ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84

Abstract: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.