公开(公告)号：US20250006678A1

公开(公告)日：2025-01-02

申请号：US18345437

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Harini Kilambi ,  Kimin Jun ,  Adel A. Elsherbini ,  John Edward Zeug Matthiesen ,  Trianggono Widodo ,  Adita Das ,  Mohit Bhatia ,  Dimitrios Antartis ,  Bhaskar Jyoti Krishnatreya ,  Rajesh Surapaneni ,  Xavier Francois Brun

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

公开(公告)号：US20240332353A1

公开(公告)日：2024-10-03

申请号：US18129737

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Xavier F. Brun ,  Rajesh Surapaneni ,  Brad S. Hamlin

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/0657 ,  H01L21/78

Abstract: Microelectronic integrated circuit package structures include a die having a dielectric die edge sidewall and a bulk silicon die edge sidewall, where the bulk silicon die edge sidewall is in substantial alignment with the dielectric die edge sidewall. The bulk silicon die edge sidewall has a plurality of scallop structures along a vertical distance of the bulk silicon die edge sidewall.