公开(公告)号：US20250118698A1

公开(公告)日：2025-04-10

申请号：US18987884

申请日：2024-12-19

Applicant: Intel Corporation

Inventor： Xavier Francois Brun ,  Sanka Ganesan ,  Holly Sawyer ,  William J. Lambert ,  Timothy A. Gosselin ,  Yuting Wang

IPC: H01L25/11 ,  H01L23/00 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.

公开(公告)号：US20250006678A1

公开(公告)日：2025-01-02

申请号：US18345437

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Harini Kilambi ,  Kimin Jun ,  Adel A. Elsherbini ,  John Edward Zeug Matthiesen ,  Trianggono Widodo ,  Adita Das ,  Mohit Bhatia ,  Dimitrios Antartis ,  Bhaskar Jyoti Krishnatreya ,  Rajesh Surapaneni ,  Xavier Francois Brun

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

公开(公告)号：US20240030142A1

公开(公告)日：2024-01-25

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/367 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/16 ,  H01L23/5384 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US10071544B2

公开(公告)日：2018-09-11

申请号：US13693151

申请日：2012-12-04

Applicant: Tokyo Electron Limited ,  INTEL CORPORATION

Inventor： Osamu Hirakawa ,  Masaru Honda ,  Akira Fukutomi ,  Takeshi Tamura ,  Jiro Harada ,  Kazutaka Noda ,  Xavier Francois Brun

IPC: B32B38/10 ,  H01L21/67 ,  B32B43/00

CPC classification number: B32B38/10 ,  B32B43/006 ,  B32B2457/14 ,  H01L21/67051 ,  H01L21/67092 ,  H01L21/67288 ,  Y10T156/11 ,  Y10T156/1189 ,  Y10T156/19 ,  Y10T156/1972

Abstract: A separation apparatus for separating a superposed substrate in which a processing target substrate and a supporting substrate are joined together with an adhesive, into the processing target substrate and the supporting substrate, includes: a first holding unit which holds the processing target substrate; a second holding unit which holds the supporting substrate; a moving mechanism which relatively moves the first holding unit or the second holding unit in a horizontal direction; a load measurement unit which measures a load acting on the processing target substrate and the supporting substrate when the processing target substrate and the supporting substrate are separated; and a control unit which controls the moving mechanism based on the load measured by the load measurement unit.

公开(公告)号：US20230134770A1

公开(公告)日：2023-05-04

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11640942B2

公开(公告)日：2023-05-02

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20220189850A1

公开(公告)日：2022-06-16

申请号：US17122061

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Xavier Francois Brun ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L23/373 ,  H01L23/498 ,  H01L23/538

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components. In some embodiments, the liner material, the inorganic fill material, and a material of the third microelectronic component may include a thermally conductive material.

公开(公告)号：US20240063179A1

公开(公告)日：2024-02-22

申请号：US17821009

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Vasanth Valavala ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Debendra Mallik ,  Feras Eid ,  Xavier Francois Brun ,  Bhaskar Jyoti Krishnatreya

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L24/20 ,  H01L24/08 ,  H01L21/568 ,  H01L24/19 ,  H01L24/06 ,  H01L2224/221 ,  H01L2224/211 ,  H01L2224/08225 ,  H01L2224/19 ,  H01L2224/0612 ,  H01L2224/06181 ,  H01L24/13 ,  H01L2224/13025 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/381

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.

公开(公告)号：US20240061194A1

公开(公告)日：2024-02-22

申请号：US17821019

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  David Hui ,  Haris Khan Niazi ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Henning Braunisch ,  Shawna M. Liff ,  Jiraporn Seangatith ,  Johanna M. Swan ,  Krishna Vasanth Valavala ,  Xavier Francois Brun ,  Feras Eid

IPC: G02B6/42

CPC classification number: G02B6/4274 ,  G02B6/4204

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.

公开(公告)号：US20230197679A1

公开(公告)日：2023-06-22

申请号：US17558457

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Jason M. Gamba ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Xiaoxuan Sun ,  Omkar G. Karhade ,  Xavier Francois Brun ,  Yonggang Li ,  Suddhasattwa Nad ,  Bohan Shan ,  Haobo Chen ,  Gang Duan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L24/16 ,  H01L24/14 ,  H01L24/73 ,  H01L24/13 ,  H01L23/5383 ,  H01L2224/16227 ,  H01L2224/14177 ,  H01L2224/73204 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01031

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.