公开(公告)号：US20220200642A1

公开(公告)日：2022-06-23

申请号：US17131872

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Abhishek AGRAWAL ,  Ritesh A. BHAT ,  Steven CALLENDER ,  Brent R. CARLTON ,  Christopher D. HULL ,  Stefano PELLERANO ,  Mustafijur RAHMAN ,  Peter SAGAZIO ,  Woorim SHIN

IPC: H04B1/04

Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.

公开(公告)号：US20240223235A1

公开(公告)日：2024-07-04

申请号：US18147721

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Ritesh A. BHAT ,  Steven CALLENDER

IPC: H04B1/44 ,  H04B1/04

CPC classification number: H04B1/44 ,  H04B1/0483

Abstract: Disclosed herein is a radio frequency (RF) circuit for a transmit/receive switch that includes an antenna coupled to a receive path through a first coupled transmission line. The antenna is also coupled to a transmit path through a second coupled transmission line. The RF circuit includes a receiver switch configured to selectively present to the receive path a high impedance or a low impedance to ground and a transmitter switch configured to selectively present to the transmit path a high impedance or a low impedance to ground. The receiver switch and/or transmitter switch may be independently supplied with a bias voltage that depends on whether the circuit is operating in a transmit mode or receive mode. The RF circuit may have improved insertion loss, bandwidth, and linearity, while also providing robustness to electrostatic discharge (ESD).

公开(公告)号：US20220416751A1

公开(公告)日：2022-12-29

申请号：US17356530

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ritesh A. BHAT ,  Woorim SHIN

IPC: H03H7/38 ,  H03H7/42

Abstract: Impedance matching circuits, impedance matching elements, and radio communication circuits are provided in this disclosure. The impedance matching circuit may include a first impedance matching element which is configured to radio communication circuit may include a modulator configured to receive an unbalanced input signal from a first input, and couple the unbalanced input signal to a first output to match an impedance of the first output to a first impedance. It may further include a second impedance matching element coupled to the first input to receive the unbalanced input signal, the second impedance matching element configured to couple the unbalanced input signal to a second output to match an impedance of the second output to a second impedance. A terminal of the first output and a terminal of the second output may be coupled to provide a balanced output signal, and the coupling may match an output impedance of the impedance matching circuit based on the first impedance and the second impedance.

公开(公告)号：US20220407544A1

公开(公告)日：2022-12-22

申请号：US17353840

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Woorim SHIN ,  Ritesh A. BHAT ,  Chuanzhao YU ,  Stefano PELLERANO

IPC: H04B1/04 ,  H04B1/30 ,  H01Q21/24

Abstract: Radio communication circuits, radio transmitters, and methods are provided in this disclosure. The radio communication circuit may include a modulator configured to provide a first modulated signal including a carrier signal at a carrier frequency, and a second modulated signal including the carrier signal at the carrier frequency. The radio communication circuit may further include a phase shift generator configured to receive a first signal based on the first modulated signal and a second signal based on the second modulated signal. The phase shift generator of the radio communication circuit may further be configured to provide a predefined phase difference between the first signal and the second signal.