-
公开(公告)号:US20240021522A1
公开(公告)日:2024-01-18
申请号:US18253945
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Tolga ACIKALIN , Tae Young YANG , Debabani CHOUDHURY , Shuhei YAMADA , Roya DOOSTNEJAD , Hosein NIKOPOUR , Issy KIPNIS , Oner ORHAN , Mehnaz RAHMAN , Kenneth P. FOUST , Christopher D. HULL , Telesphor KAMGAING , Omkar KARHADE , Stefano PELLERANO , Peter SAGAZIO , Sai VADLAMANI
IPC: H01L23/538 , H01L25/065 , H01L23/00 , H01L23/66 , H01L23/498 , H01Q1/22
CPC classification number: H01L23/5381 , H01L25/0652 , H01L24/16 , H01L23/66 , H01L23/49822 , H01Q1/2283 , H01L24/81 , H01L2924/14222 , H01L2924/1431 , H01L2223/6677 , H01L2223/6616 , H01L2223/6655 , H01L2224/16235 , H01L2224/16146
Abstract: Various devices, systems, and/or methods perform wireless chip to chip high speed data transmission. Strategies for such transmission include use of improved microbump antennas, wireless chip to chip interconnects, precoding and decoding strategies, channel design to achieve spatial multiplexing gain in line of sight transmissions, open cavity chip design for improved transmission, and/or mixed signal channel equalization.
-
公开(公告)号:US20240097693A1
公开(公告)日:2024-03-21
申请号:US17933512
申请日:2022-09-20
Applicant: Intel Corporation
Inventor: Somnath KUNDU , Amy L. WHITCOMBE , Stefano PELLERANO , Peter SAGAZIO , Brent CARLTON
CPC classification number: H03M1/1014 , H04B1/40
Abstract: An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.
-
公开(公告)号:US20220200642A1
公开(公告)日:2022-06-23
申请号:US17131872
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Abhishek AGRAWAL , Ritesh A. BHAT , Steven CALLENDER , Brent R. CARLTON , Christopher D. HULL , Stefano PELLERANO , Mustafijur RAHMAN , Peter SAGAZIO , Woorim SHIN
IPC: H04B1/04
Abstract: Various aspects provide a transceiver and a communication device including the transceiver. In an example, the transceiver includes an amplifier circuit including an amplifier stage with an adjustable degeneration component, the amplifier stage configured to amplify a received input signal with an adjustable gain, an adjustable feedback component coupled to the amplifier stage; and a controller coupled to the amplifier stage and to the adjustable feedback component and configured to adjust the adjustable feedback component based on an adjustment of the adjustable degeneration component.
-
公开(公告)号:US20240113698A1
公开(公告)日:2024-04-04
申请号:US17956844
申请日:2022-09-30
Applicant: Intel Corporation
Inventor: Richard DORRANCE , Peter SAGAZIO , Renzhi LIU , Hechen WANG , Deepak DASALUKUNTE , Brent R. CARLTON
IPC: H03H17/02
CPC classification number: H03H17/02 , H03H2218/10
Abstract: A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.
-
5.
公开(公告)号:US20220200750A1
公开(公告)日:2022-06-23
申请号:US17124536
申请日:2020-12-17
Applicant: Intel Corporation
Inventor: Peter SAGAZIO , Chun C. LEE , Stefano PELLERANO , Christopher D. HULL
Abstract: Various aspects of this disclosure provide a receiver. The receiver may include a down-converter configured to down-convert a received communication signal at a predefined carrier frequency, with a reference signal received from a reference signal generator, and a processor configured to perform a signal quality detection to identify a signal quality metric of the received communication signal at the predefined carrier frequency, and to provide a frequency adjusting signal to the reference signal generator to change the frequency of the reference signal based on the performed signal quality detection to identify the signal quality metric of the received communication signal at the predefined carrier frequency.
-
-
-
-